FPGA implementation of EEG based hardware optimized data encryption technique for IoT applications

Abstract

This paper has presented a new electroencephalogram (EEG)-based encryption technique for enhancing image data security using an FPGA implementation for IoT applications. The technique has used EEG datasets to create 64-bit keys, which have undergone testing using the NIST SP 800-22 test suite for randomness check. The generated keys have been combined with the image data and subjected to substitution and LFSR-based permutation in a proposed order. The proposed method has implemented the RTL design on a Virtex-7 FPGA device, with careful selection of rounds to optimize encryption process efficiency. The hardware expenditure per round on the FPGA device has been assessed to determine the optimal limit on the number of rounds, and the simulation results have been validated using MATLAB. The parameters Number of Changing Pixel Rate (NPCR) and Unified Averaged Changed Intensity (UACI) have been calculated as 99.5697% and 33.4776%, respectively, while the entropy of the encrypted image is 7.95, indicating that the suggested approach exhibits greater resilience against differential attacks. The proposed method has achieved a maximum operating frequency of 815.395 MHz and efficiency of 5.623 Mbps/slice on Virtex-7 FPGA device which has exhibited a 49.95% increase in the maximum frequency of operation and a 7.11% gain in efficiency when compared with the state of the art. These improvements have been important for reducing the encryption time and efficiently utilizing the hardware with the optimum number of slices.