A VRO-based TDC with a constant timing resolution ratio between coarse-tuning and fine-tuning stages for a light sensor application

Abstract

This study designs a vernier ring oscillator (VRO)-based time-to-digital converter (TDC), ensuring a proportional relationship between the timing resolutions of the coarse-tuning stage (CTS) and fine-tuning stage (FTS) under process, voltage, and temperature (PVT) variations. The design allows flexibility in extending the bit number to a wide input range during CTS. The timing resolutions of CTS and FTS were defined by the rise and fall times. Therefore, the timing ratio between CTS and FTS of VRO-based TDC remained constant under the PVT variations. This 14-bit TDC was fabricated using a 0.18 μm standard CMOS process with a core area of 45 μm × 200 μm. The measured timing resolution of the proposed VRO-based TDC was 125 ps, and the input range was from 10 to 200 ns. The DNL and INL values were less than ±0.244 and ± 0.336 LSB, respectively. The proposed VRO-based TDC was also integrated with a light sensor for Internet of Things applications.