Y. Yan , M. Rack , M. Vanbrabant , M. Nabet , A. Goebel , P. Clifton , J.-P. Raskin
{"title":"Traps characterization in RF SOI substrates including a buried SiGe layer","authors":"Y. Yan , M. Rack , M. Vanbrabant , M. Nabet , A. Goebel , P. Clifton , J.-P. Raskin","doi":"10.1016/j.sse.2025.109103","DOIUrl":null,"url":null,"abstract":"<div><div>This work analyzes the interface traps density (<em>D</em><sub>it</sub>) at the SiO<sub>2</sub>/SiGe interface of a buried SiGe stressor SOI substrate, and demonstrates the impact of those traps on the effective resistivity (<em>ρ</em><sub>eff</sub>) of the substrate. The <em>C-V</em> behavior of MOS capacitors and the RF insertion loss along coplanar waveguide transmission lines on various substrates are measured. TCAD simulations are employed to interpret the traps characteristics and to forecast the RF performance of a buried SiGe stressor SOI wafer having a high resistivity handle Si substrate. The results demonstrate that thanks to the interface traps introduced by the SiGe layer the substrate effective resistivity (<em>ρ</em><sub>eff</sub>) is enhanced.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109103"},"PeriodicalIF":1.4000,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0038110125000486","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This work analyzes the interface traps density (Dit) at the SiO2/SiGe interface of a buried SiGe stressor SOI substrate, and demonstrates the impact of those traps on the effective resistivity (ρeff) of the substrate. The C-V behavior of MOS capacitors and the RF insertion loss along coplanar waveguide transmission lines on various substrates are measured. TCAD simulations are employed to interpret the traps characteristics and to forecast the RF performance of a buried SiGe stressor SOI wafer having a high resistivity handle Si substrate. The results demonstrate that thanks to the interface traps introduced by the SiGe layer the substrate effective resistivity (ρeff) is enhanced.
期刊介绍：
It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.
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