An Accurate Assessment of Chip-Package Interaction is a Key Factor for Designing Resilient 3D IC Systems

Novel approach for assessment of the effect of temperature and chip-package interaction (CPI) induced stress on performance and reliability of ICs with 2.5D/3D architectures is presented. A developed physics-based model and a multiphysics EDA tool-prototype analyze thermal, and thermomechanical problems during package assembly and chip operation. The tool employs effective anisotropic thermalmechanical properties methodology that accurately represents non-uniformity within a die or a layer, and significantly boosts computational performance by avoiding complex geometries. An implemented link between layout analysis tools and the multiphysics thermal mechanical tool enables to perform reliability check within the design flow. The developed stress simulation flow takes into account multiscale stress variations from a package macro-scale to an interconnect segment and transistor nano-scale. The obtained across-chip temperature and stress fields are used for calculating the variations in transistors electrical characteristics, and for analysis of potential cracking locations in the interconnect layers.