Thermal Stress Tracking in Multi-Die 3D Stacking Structure by Finite Element Analysis

3D packaging technology, which has advantages such as power consumption and delay reduction, high integration, high bandwidth, and reduced form factor compared to conventional 2D packaging, has been actively studied as promising technology in the semiconductor package field. However, there are many issues in 3D stacking package such as IMD crack, interface delamination, TSV void, liner / barrier damage of TSV, thin die crack, and solder consumption etc. And these issues degrade package reliability. Therefore, in this paper, we propose a method to analyze the reliability problem from the viewpoint of stress through the 3D stacking package simulation and to improve the reliability. In order to carry out the computer simulation, a 3D structure in which a multi die is stacked with four layers is modeled and a thermal cycling test according to the JEDEC22-A104 standard is simulated. Each layer was connected to the RDL layer of the upper layer through a microsolder and the TMV filled with copper through a via hole in the lower layer mold. And the stress occurs in the package according to the rapid temperature change of the thermal cycle. As a result, the maximum stress occurred in the microsolders located at the bottom layer, especially at the part contacting the TMVs. This is consistent with the tendency of cracks, which is a problem that is often observed in microsolder and TMV. In addition, maximum strain and minimum stress were generated in the uppermost EMC layer Because the heat load was directly expressed as deformation not accumulating the stress.