M. Goto, J. D. Vos, T. Watabe, K. Hagiwara, M. Nanba, Y. Iguchi, E. Higurashi, Y. Honda, T. Saraya, M. Kobayashi, H. Toshiyoshi, T. Hiramoto
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Triple-Layering Technology for Pixel-Parallel CMOS Image Sensors Developed by Hybrid Bonding of SOI Wafers
We report a triple-layering technology for pixelparallel CMOS image sensors. Photodiodes (PDs), logic circuits, and 16-bit pulse counters are developed on silicon-on-insulator (SOI) wafers, and they are three-dimensionally integrated within every pixel by using hybrid bonding through damascened Au electrodes of 5 pm in diameter in a SiO2 insulator. The developed triple-stacked wafers are confirmed to have no voids or separation of layers even after the removal of the handle layer, thereby demonstrating the feasibility of multi-layered imaging devices for the next-generation video systems.
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