Comprehensive analysis of MOSFET threshold voltage extraction method considering DIBL effect from 300 K down to 10 K

Abstract

It is well known that different threshold voltage (V_th) extraction methods exhibit inconsistencies with respect to different drain voltage (V_d). This inconsistency becomes disruptive when temperature is considered for cryogenic applications such as quantum computing. This investigation examines various V_th extraction methods from room down to cryogenic temperatures, with a particular emphasis on how different V_d values combined with extraction methods behave as temperature decreases. For the first time, we find that the square root I_d method maintains consistency regardless of V_d, from 300 K all the way down to 10 K is identified. This provides a good insight into how the Drain-Induced Barrier Lowering (DIBL) effect changes with temperature, and positions the square root I_d method as a reliable tool for V_th extraction in cryogenic temperature.