A. Ortiz-Conde , V.C.P. Silva , P.G.D. Agopian , J.A. Martino , F.J. García-Sánchez
{"title":"Some considerations about Lambert W function-based nanoscale MOSFET charge control modeling","authors":"A. Ortiz-Conde , V.C.P. Silva , P.G.D. Agopian , J.A. Martino , F.J. García-Sánchez","doi":"10.1016/j.sse.2025.109080","DOIUrl":null,"url":null,"abstract":"<div><div>The unwanted low-level doping present in supposedly undoped MOSFET channels has a significant effect on charge control and Lambert W function-based inversion charge MOSFET models, as well as on subsequent drain current models. We show that the hypothetical intrinsic MOSFET channel approximation, often used to describe a nominally undoped channel, produces significant errors, even for the low-level concentrations resulting from unintentional doping. We show that the traditional charge control model, which mathematically describes the gate voltage as the sum of one linear and one logarithmic term of the inversion charge, is only valid for the hypothetically intrinsic case. However, it may still be used for nominally undoped but unintentionally low-doped channel devices within the region of operation where the majority carriers are the dominant charge. With this in mind, we present here a better approximation of the nominally undoped MOSFET channel surface potential. We also propose an improved modified expression that describes the gate voltage as the sum of one linear and two logarithmic terms of the inversion charge. A new approximate drain current control formulation is also proposed to account for parasitic series resistance and/or mobility degradation. The new model agrees reasonably well with measurement data from nominally undoped vertically stacked GAA Si Nano Sheet MOSFETs.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109080"},"PeriodicalIF":1.4000,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0038110125000255","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
The unwanted low-level doping present in supposedly undoped MOSFET channels has a significant effect on charge control and Lambert W function-based inversion charge MOSFET models, as well as on subsequent drain current models. We show that the hypothetical intrinsic MOSFET channel approximation, often used to describe a nominally undoped channel, produces significant errors, even for the low-level concentrations resulting from unintentional doping. We show that the traditional charge control model, which mathematically describes the gate voltage as the sum of one linear and one logarithmic term of the inversion charge, is only valid for the hypothetically intrinsic case. However, it may still be used for nominally undoped but unintentionally low-doped channel devices within the region of operation where the majority carriers are the dominant charge. With this in mind, we present here a better approximation of the nominally undoped MOSFET channel surface potential. We also propose an improved modified expression that describes the gate voltage as the sum of one linear and two logarithmic terms of the inversion charge. A new approximate drain current control formulation is also proposed to account for parasitic series resistance and/or mobility degradation. The new model agrees reasonably well with measurement data from nominally undoped vertically stacked GAA Si Nano Sheet MOSFETs.
期刊介绍:
It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.