Degradation mechanisms for static and dynamic characteristics in 1.2 kV 4H-SiC MOSFETs under repetitive short-circuit tests

Abstract

In this paper, repetitive short-circuit (RSC) tests are conducted at off-state and on-state gate-source voltages (V_GS,OFF/V_GS,ON) of −4/+15 V, −4/+19 V and 0/+19 V, respectively, to investigate the degradation behaviors of 1.2 kV 4H-SiC MOSFETs. Combining experimental and simulation results, it is found that trapped electrons or holes in the gate oxide during the avalanche process are the main degradation mechanism for the static parameters. This results in increases of 0.4 V and 3.0 mΩ in V_TH and R_DS,ON, respectively, at V_GS,OFF/V_GS,ON = −4/+19 V; 0.45 V and 4.1 mΩ at V_GS,OFF/V_GS,ON = 0/+19 V; and decreases of 0.69 V and 3.2 mΩ at V_GS,OFF/V_GS,ON = −4/+15 V after 240 short-circuit (SC) tests. The dynamic characteristics of the device under test, including C_GS, C_DS, C_GD also degrade. The trapped holes in the gate oxide above the JFET region lead to a thinner depletion region and an obvious increase in C_GD. Furthermore, the gate leakage current under high reverse gate bias is affected by the RSC tests, primarily attributed to trapped electrons hopping to the poly-Si/SiO₂ interface via defect states.