Improvement of gate oxide breakdown through STI structure Modification in DRAM

IF 1.4 4区 物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Solid-state Electronics Pub Date : 2025-01-09 DOI:10.1016/j.sse.2025.109064
Dong-Sik Park , Ji-Hoon Chang , Su-Ho Shin , Chang-Sik Kim , Yongsoo Ahn , Byoungdeog Choi
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Abstract

This paper focuses on investigating the origin of the vulnerability and proposing improvement strategies for gate oxide (Gox) breakdown in the core area of dynamic random access memory (DRAM) products. The shallow trench isolation (STI) area in 15-nm DRAM intricately comprises a triple-layer structure: sidewall oxide, nitride liner, and trench oxide. The existing structure had a high protrusion of the nitride liner, disrupting the gas flow during Gox deposition and resulting in a relatively thin thickness at the active corners. Additionally, when the gate voltage is applied, the angular shape of the active Si area led to a concentration of the electric field in the corner area. These two structural characteristics were recognized as the causes that render the active corner area vulnerable to Gox breakdown failure. By developing new wet-etching processes for the active and STI structures, we can significantly improve Gox breakdown. We applied a phosphoric acid process to improve the high protrusion structure of the nitride liner and used a new solution process to make the active corner more rounded. We validated the enhancement through the application to actual products and verified it by electrical results. Ultimately, this approach serves as a crucial clue for the continued scaling of DRAM core transistors.
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来源期刊
Solid-state Electronics
Solid-state Electronics 物理-工程:电子与电气
CiteScore
3.00
自引率
5.90%
发文量
212
审稿时长
3 months
期刊介绍: It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.
期刊最新文献
Editorial Board Recent progress in bipolar and heterojunction bipolar transistors on SOI Expanding the potential of Zn0.15Sn0.85(Se0.95S0.05)2 crystals for applications in near-infrared optoelectronics, sensing, and Van der Waals heterojunctions Intense near-infrared electroluminescence properties from ZnO:Yb LED Traps characterization in RF SOI substrates including a buried SiGe layer
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