Pub Date : 2011-03-06DOI: 10.1109/CHANGE.2011.6172451
Faizal Arya Samman, F. Philipp, M. Glesner
A concept for reconfigurable communication infrastructure for networked control systems is presented in this paper. The communication infrastructure consists of two communication protocols, i.e. wireless communication and wired communication protocols. The concept is dedicated for a hard real-time distributed parameter control system, where each local control module is implemented as a platform with multiple/interconnected reconfigurable and programmable devices such as Field-programmable Gate Arrays (FPGAs) and microcontrollers. Adaptive networked multiprocessing algorithms can be further mapped onto the platform for specific real-time control applications. Data exchanges between multiple control units on a hardware platform are controlled by multicast-enabled switches that are also implemented on the FPGA devices. Data exchanges between platforms in a more complex system are controlled by a wireless standard communication protocol. The exchanged data can be sensor signals, actuating signals and system parameters. A bit-level parallel handshaking interface (PHI) adapter is introduced to handle the inter-switch data communication between the FPGA devices.
{"title":"Reconfigurable interconnect infrastructure for multi-FPGA-based adaptive multiprocessing systems","authors":"Faizal Arya Samman, F. Philipp, M. Glesner","doi":"10.1109/CHANGE.2011.6172451","DOIUrl":"https://doi.org/10.1109/CHANGE.2011.6172451","url":null,"abstract":"A concept for reconfigurable communication infrastructure for networked control systems is presented in this paper. The communication infrastructure consists of two communication protocols, i.e. wireless communication and wired communication protocols. The concept is dedicated for a hard real-time distributed parameter control system, where each local control module is implemented as a platform with multiple/interconnected reconfigurable and programmable devices such as Field-programmable Gate Arrays (FPGAs) and microcontrollers. Adaptive networked multiprocessing algorithms can be further mapped onto the platform for specific real-time control applications. Data exchanges between multiple control units on a hardware platform are controlled by multicast-enabled switches that are also implemented on the FPGA devices. Data exchanges between platforms in a more complex system are controlled by a wireless standard communication protocol. The exchanged data can be sensor signals, actuating signals and system parameters. A bit-level parallel handshaking interface (PHI) adapter is introduced to handle the inter-switch data communication between the FPGA devices.","PeriodicalId":103211,"journal":{"name":"2011 1st International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-Oriented Environments (CHANGE)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116712107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-06DOI: 10.1109/CHANGE.2011.6172452
Simone Campanoni, Luca Rocchini
Object-code virtualization, commonly used to achieve software portability, relies on a virtual execution environment, typically comprising an interpreter used for initial execution of methods, and a JIT for native code generation. The availability of multiple processors on current architectures makes it attractive to perform dynamic compilation in parallel with application execution. The pipeline model is appealing for the compilation tasks that dynamic compilers need to perform, but it can bring deadlock issues when static memories are exploited by the running program. This research suggests a solution that both solves the mentioned problem and reduces the unnecessary compiler threads used to handle static memories. The proposed solution is a self-aware runtime system that both it is able to detect/avoid deadlocks and it adapts the number of compilation threads needed to handle static memories to the current workload.
{"title":"Static memory management within bytecode languages on multicore systems","authors":"Simone Campanoni, Luca Rocchini","doi":"10.1109/CHANGE.2011.6172452","DOIUrl":"https://doi.org/10.1109/CHANGE.2011.6172452","url":null,"abstract":"Object-code virtualization, commonly used to achieve software portability, relies on a virtual execution environment, typically comprising an interpreter used for initial execution of methods, and a JIT for native code generation. The availability of multiple processors on current architectures makes it attractive to perform dynamic compilation in parallel with application execution. The pipeline model is appealing for the compilation tasks that dynamic compilers need to perform, but it can bring deadlock issues when static memories are exploited by the running program. This research suggests a solution that both solves the mentioned problem and reduces the unnecessary compiler threads used to handle static memories. The proposed solution is a self-aware runtime system that both it is able to detect/avoid deadlocks and it adapts the number of compilation threads needed to handle static memories to the current workload.","PeriodicalId":103211,"journal":{"name":"2011 1st International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-Oriented Environments (CHANGE)","volume":"29 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126246703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-06DOI: 10.1109/CHANGE.2011.6172448
D. Bartolini, F. Cancare, M. Carminati, D. Sciuto
Since the birth of the Evolvable Hardware (EHW) research field (1993), many FPGA-based evolvable hardware techniques have been devised and proposed to the scientific community. Even if newer EHW systems introduce improvements and new features with respect to the older ones, in most cases they are still based on outdated FPGAs. Thus, they are often limited by the amount of available resources and by the capabilities of the devices used. This paper describes an EHW system based on a Xilinx Virtex-4 FPGA able to exploit features like the direct bitstream manipulation and the two-dimensional dynamic reconfiguration mechanism. Such system has been introduced in 2009 and has been refined in order to cope with real-world applications like the classification problem addressed in this paper.
{"title":"HERA: Hardware evolution over reconfigurable architectures","authors":"D. Bartolini, F. Cancare, M. Carminati, D. Sciuto","doi":"10.1109/CHANGE.2011.6172448","DOIUrl":"https://doi.org/10.1109/CHANGE.2011.6172448","url":null,"abstract":"Since the birth of the Evolvable Hardware (EHW) research field (1993), many FPGA-based evolvable hardware techniques have been devised and proposed to the scientific community. Even if newer EHW systems introduce improvements and new features with respect to the older ones, in most cases they are still based on outdated FPGAs. Thus, they are often limited by the amount of available resources and by the capabilities of the devices used. This paper describes an EHW system based on a Xilinx Virtex-4 FPGA able to exploit features like the direct bitstream manipulation and the two-dimensional dynamic reconfiguration mechanism. Such system has been introduced in 2009 and has been refined in order to cope with real-world applications like the classification problem addressed in this paper.","PeriodicalId":103211,"journal":{"name":"2011 1st International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-Oriented Environments (CHANGE)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125589240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-06DOI: 10.1109/CHANGE.2011.6172449
F. Sironi, Andrea Cuoccio
Modern computing systems contain more and more processing units that are increasingly difficult to exploit; statically optimizing software for all hardware architectures and execution scenarios pose serious challenges. Self-aware adaptive computing systems are capable of adapting their behavior thousands of times per second to accomplish given goals despite living and working in an unpredictable environment whose condition can vary continually. Changing the behavior of a computing system may benefit a wide variety of fields, raging from the embedded world (e.g., smart phones) to the supercomputers world (e.g., clusters) and is particularly useful for meeting performance, power consumption, and resource consumption challenges. With this paper we show the impact of using self-aware adaptive applications running on heterogeneous computing systems featuring diverse processing units. The operating system will answer requests for functionalities by choosing at runtime the best suiting implementations. During the applications lifetime, their performances are monitored and, if necessary, active implementations are changed using a hot-swap mechanism. This work presents our vision for self-aware adaptive applications, focusing its attention on a hot-swap mechanism proving its effectiveness using a cryptographic secure hash algorithm executed on the diverse processing units of a heterogeneous computing system.
{"title":"Self-aware adaptation via implementation hot-swap for heterogeneous computing","authors":"F. Sironi, Andrea Cuoccio","doi":"10.1109/CHANGE.2011.6172449","DOIUrl":"https://doi.org/10.1109/CHANGE.2011.6172449","url":null,"abstract":"Modern computing systems contain more and more processing units that are increasingly difficult to exploit; statically optimizing software for all hardware architectures and execution scenarios pose serious challenges. Self-aware adaptive computing systems are capable of adapting their behavior thousands of times per second to accomplish given goals despite living and working in an unpredictable environment whose condition can vary continually. Changing the behavior of a computing system may benefit a wide variety of fields, raging from the embedded world (e.g., smart phones) to the supercomputers world (e.g., clusters) and is particularly useful for meeting performance, power consumption, and resource consumption challenges. With this paper we show the impact of using self-aware adaptive applications running on heterogeneous computing systems featuring diverse processing units. The operating system will answer requests for functionalities by choosing at runtime the best suiting implementations. During the applications lifetime, their performances are monitored and, if necessary, active implementations are changed using a hot-swap mechanism. This work presents our vision for self-aware adaptive applications, focusing its attention on a hot-swap mechanism proving its effectiveness using a cryptographic secure hash algorithm executed on the diverse processing units of a heterogeneous computing system.","PeriodicalId":103211,"journal":{"name":"2011 1st International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-Oriented Environments (CHANGE)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114513625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-03-06DOI: 10.1109/CHANGE.2011.6172450
Oliver Arnold, G. Fettweis
This paper introduces a new battery-aware dynamic task scheduling approach for heterogeneous MPSoCs. A collector, a dc-dc converter and a battery module are introduced in the system. Additionally, a configurable and flexible load can be specified for modeling further components. Battery-aware modes of operation are newly introduced to extend battery lifetime. Therefore, processing element allocation, task scheduling and data transfers are dynamically performed with respect to the current battery status. In comparison to battery independent dynamic power management we are able to show that battery lifetime is extended.
{"title":"Self-aware heterogeneous MPSoC with dynamic task scheduling for battery lifetime extension","authors":"Oliver Arnold, G. Fettweis","doi":"10.1109/CHANGE.2011.6172450","DOIUrl":"https://doi.org/10.1109/CHANGE.2011.6172450","url":null,"abstract":"This paper introduces a new battery-aware dynamic task scheduling approach for heterogeneous MPSoCs. A collector, a dc-dc converter and a battery module are introduced in the system. Additionally, a configurable and flexible load can be specified for modeling further components. Battery-aware modes of operation are newly introduced to extend battery lifetime. Therefore, processing element allocation, task scheduling and data transfers are dynamically performed with respect to the current battery status. In comparison to battery independent dynamic power management we are able to show that battery lifetime is extended.","PeriodicalId":103211,"journal":{"name":"2011 1st International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-Oriented Environments (CHANGE)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125471546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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