Pub Date : 2019-11-30DOI: 10.21742/WJWDE.2019.3.1.01
M. Adegboye
Aquaculture represents an important food production system with high quality protein for human consumption. The contributions of aquaculture to the world’s total fish production cannot be over emphasized, however, however, feeding is the major challenges facing in aquaculture system. Thus, to address this, development of intelligent fish feeding regime system based on vibration analysis is proposed in this paper. This was accomplished with the use of a novel 8-directional Chain Code generator algorithm developed for the extraction of signals from accelerometer for the escape and feeding activities. For the escape activity, x- and z-coordinate were selected, while x- and y- coordinate were chosen for the feeding behavioural activity. The choice of coordinate selects is based on the fact that escape activity exists more between x- and z- coordinate, while feeding activity more exists between x- and y- coordinate. The set of sequence features obtained was further processed using Discrete Fourier Transform in analysing the movement boundary. The results obtained shows that developed classifier using Fourier Descriptors obtained from Chain Code is more sufficient for the recognition of different movement patterns than Fourier Descriptors obtained from movement boundary.
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Pub Date : 2019-11-30DOI: 10.21742/WJWDE.2019.3.1.03
Jungseok Cho
Mobile devices designed for IoT exploit a variety of system optimization techniques to maximize performance while reducing power consumption. These technologies apply to communication modules, to memory system, and to the central processing unit. Most of the technologies are developed and applied at the design stage of the system, but not many technologies are applied at the system integration stage. In the system integration stage, the major power consuming parts are the communication part and the memory part. Since communication has a lot of variables depending on the network environment, there are some limited technologies available, but in the case of memory, a large benefit can be obtained depending on the technology applied. Mobile or IoT system’s memory structures can be classified in many different ways, of which we focus on multi-bank memory. Multi-bank memory refers to a method of dividing a large memory into several smaller memories. Using multi-bank memory can reduce operating power consumption and support parallel memory accesses, resulting in improved performance, which is often used in commercial products. A compiler should generate the access instruction and data placement properly. Therefore, the system performance is determined by the compiler performance. In this paper, we introduce a compiler optimization technique for multi-bank memory to overcome the compiler performance. The proposed technique can improve energy consumption by up to 20% in multi-bank memory systems.
{"title":"An Automatic Array Distribution Technique for Multi-Bank Memory of High Performance IoT Systems","authors":"Jungseok Cho","doi":"10.21742/WJWDE.2019.3.1.03","DOIUrl":"https://doi.org/10.21742/WJWDE.2019.3.1.03","url":null,"abstract":"Mobile devices designed for IoT exploit a variety of system optimization techniques to maximize performance while reducing power consumption. These technologies apply to communication modules, to memory system, and to the central processing unit. Most of the technologies are developed and applied at the design stage of the system, but not many technologies are applied at the system integration stage. In the system integration stage, the major power consuming parts are the communication part and the memory part. Since communication has a lot of variables depending on the network environment, there are some limited technologies available, but in the case of memory, a large benefit can be obtained depending on the technology applied. Mobile or IoT system’s memory structures can be classified in many different ways, of which we focus on multi-bank memory. Multi-bank memory refers to a method of dividing a large memory into several smaller memories. Using multi-bank memory can reduce operating power consumption and support parallel memory accesses, resulting in improved performance, which is often used in commercial products. A compiler should generate the access instruction and data placement properly. Therefore, the system performance is determined by the compiler performance. In this paper, we introduce a compiler optimization technique for multi-bank memory to overcome the compiler performance. The proposed technique can improve energy consumption by up to 20% in multi-bank memory systems.","PeriodicalId":137201,"journal":{"name":"World Journal of Wireless Devices and Engineering","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129878388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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