K. C. Chen, Andy Lan, Richer Yang, V. Chen, Shulu Wang, Stella Zhang, Xiang-ru Xu, A. Yang, Sam Liu, Xiaolong Shi, Angmar Li, S. Hsu, S. Baron, Gary Zhang, Rachit Gupta
As technology continues to scale aggressively, Sub-Resolution Assist Features (SRAF) are becoming an increasingly key resolution enhancement technique (RET) to maximize the process window enhancement. For the past few technology generations, lithographers have chosen to use a rules-based (RB-SRAF) or a model-based (MB-SRAF) approach to place assist features on the design. The inverse lithography solution, which provides the maximum process window entitlement, has always been out of reach for full-chip applications due to its very high computational cost. ASML has developed and demonstrated a deep learning SRAF placement methodology, Newron™ SRAF, which can provide the performance benefit of an inverse lithography solution while meeting the cycle time requirements for full-chip applications [1]. One of the biggest challenges for a deep learning approach is pattern selection for neural network training. To ensure pattern coverage for maximum accuracy while maintaining turn-around time (TAT,) a deep-learning-based Auto Pattern Selection (APS) tool is evaluated. APS works in conjunction with Newron SRAF to provide the optimal lithography solution. In this paper, Newron SRAF is used on a DRAM layer. A Deep Convolutional Neural Network (DCNN) is trained using the target images and Continuous Transmission Mask (CTM) images. CTM images are gray tone images that are fully optimized by the Tachyon inverse mask optimization engine. Representative patterns selected by APS are used to train the neural network. The trained neural network generates SRAFs on the full-chip and then Tachyon OPC+ is performed to correct main and SRAF simultaneously. The neural network trained by APS patterns is compared with those trained by patterns from manual selection and multiple random selections to demonstrate its robustness on pattern coverage. Tachyon Hierarchical OPC+ (HScan+) is used to apply Newron SRAF at full-chip level in order to keep consistency and increase speed. Full-chip simulation results from Newron SRAF are compared with the baseline OPC flow using RBSRAF and MB-SRAF. The Newron SRAF flow shows significant improvements in NILS and PV band over the baseline flows. This whole flow including APS, Newron SRAF and full-chip HScan+ OPC enables the inverse mask optimization on full-chip level to achieve superior mask performance with production-affordable TAT.
{"title":"Full-chip application of machine learning SRAFs on DRAM case using auto pattern selection","authors":"K. C. Chen, Andy Lan, Richer Yang, V. Chen, Shulu Wang, Stella Zhang, Xiang-ru Xu, A. Yang, Sam Liu, Xiaolong Shi, Angmar Li, S. Hsu, S. Baron, Gary Zhang, Rachit Gupta","doi":"10.1117/12.2524051","DOIUrl":"https://doi.org/10.1117/12.2524051","url":null,"abstract":"As technology continues to scale aggressively, Sub-Resolution Assist Features (SRAF) are becoming an increasingly key resolution enhancement technique (RET) to maximize the process window enhancement. For the past few technology generations, lithographers have chosen to use a rules-based (RB-SRAF) or a model-based (MB-SRAF) approach to place assist features on the design. The inverse lithography solution, which provides the maximum process window entitlement, has always been out of reach for full-chip applications due to its very high computational cost. ASML has developed and demonstrated a deep learning SRAF placement methodology, Newron™ SRAF, which can provide the performance benefit of an inverse lithography solution while meeting the cycle time requirements for full-chip applications [1]. One of the biggest challenges for a deep learning approach is pattern selection for neural network training. To ensure pattern coverage for maximum accuracy while maintaining turn-around time (TAT,) a deep-learning-based Auto Pattern Selection (APS) tool is evaluated. APS works in conjunction with Newron SRAF to provide the optimal lithography solution. In this paper, Newron SRAF is used on a DRAM layer. A Deep Convolutional Neural Network (DCNN) is trained using the target images and Continuous Transmission Mask (CTM) images. CTM images are gray tone images that are fully optimized by the Tachyon inverse mask optimization engine. Representative patterns selected by APS are used to train the neural network. The trained neural network generates SRAFs on the full-chip and then Tachyon OPC+ is performed to correct main and SRAF simultaneously. The neural network trained by APS patterns is compared with those trained by patterns from manual selection and multiple random selections to demonstrate its robustness on pattern coverage. Tachyon Hierarchical OPC+ (HScan+) is used to apply Newron SRAF at full-chip level in order to keep consistency and increase speed. Full-chip simulation results from Newron SRAF are compared with the baseline OPC flow using RBSRAF and MB-SRAF. The Newron SRAF flow shows significant improvements in NILS and PV band over the baseline flows. This whole flow including APS, Newron SRAF and full-chip HScan+ OPC enables the inverse mask optimization on full-chip level to achieve superior mask performance with production-affordable TAT.","PeriodicalId":208195,"journal":{"name":"Optical Microlithography XXXII","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121394735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chemically amplified resists undergo various chemical phenomena during the photolithography process such as exposure, post-exposure bake (PEB), and development. These chemical changes induce various stresses causing the deformation of exposed region of photoresist. It is imperative to include these deformations in the modeling of lithographic processes especially for negative tone development (NTD) process, where an exposed and deformed part of the resist stays on the substrate after development. We use rigorous physical model to express the stresses induced by voids created in resist by evaporation of the protecting species. Finite Element method (FEM) is then used to solve three-dimensional elastic deformation equations for resist during PEB and development. The deformation of resist is studied for both one-dimensional gratings and two-dimensional contact holes with varying pitch and optical doses, and we discuss how different modes of deformation are important to be considered in the lithography simulations in order to reduce the critical dimensions’ (CD) computation error. Finally, we briefly introduce a compact model where Fourier series are used to find the exact analytical solution of elastic deformation equations. The results of compact model are compared with the rigorous FEM solution. The compact model is suitable for full chip lithography simulations due to it being numerically fast operations and results comparable to full-physics rigorous simulations.
{"title":"Physical and compact modeling of resist deformation (Conference Presentation)","authors":"Gurdaman S. Khaira, Y. Granik, K. Adam, G. Fenger","doi":"10.1117/12.2515128","DOIUrl":"https://doi.org/10.1117/12.2515128","url":null,"abstract":"Chemically amplified resists undergo various chemical phenomena during the photolithography process such as exposure, post-exposure bake (PEB), and development. These chemical changes induce various stresses causing the deformation of exposed region of photoresist. It is imperative to include these deformations in the modeling of lithographic processes especially for negative tone development (NTD) process, where an exposed and deformed part of the resist stays on the substrate after development.\u0000We use rigorous physical model to express the stresses induced by voids created in resist by evaporation of the protecting species. Finite Element method (FEM) is then used to solve three-dimensional elastic deformation equations for resist during PEB and development. The deformation of resist is studied for both one-dimensional gratings and two-dimensional contact holes with varying pitch and optical doses, and we discuss how different modes of deformation are important to be considered in the lithography simulations in order to reduce the critical dimensions’ (CD) computation error. Finally, we briefly introduce a compact model where Fourier series are used to find the exact analytical solution of elastic deformation equations. The results of compact model are compared with the rigorous FEM solution. The compact model is suitable for full chip lithography simulations due to it being numerically fast operations and results comparable to full-physics rigorous simulations.","PeriodicalId":208195,"journal":{"name":"Optical Microlithography XXXII","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131800524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We explore role of software modeling in semiconductor manufacturing and contrast it with the roles that modeling plays in other fields of human activity. Major trends and challenges in physical and compact process modeling are discussed. We contemplate complexities arising from their multi-dimensional nature. The landscape of Optical Proximity Correction and satellite applications is surveyed. Instructive examples are collected that demonstrate shortcomings of our intuition while dealing with complex systems and parameter interactions. We ponder over the scientific and business opportunities of new promising techniques and prospective applications.
{"title":"Software in semiconductor manufacturing: peripeteias and prospects (Conference Presentation)","authors":"Y. Granik","doi":"10.1117/12.2514761","DOIUrl":"https://doi.org/10.1117/12.2514761","url":null,"abstract":"We explore role of software modeling in semiconductor manufacturing and contrast it with the roles that modeling plays in other fields of human activity. Major trends and challenges in physical and compact process modeling are discussed. We contemplate complexities arising from their multi-dimensional nature. The landscape of Optical Proximity Correction and satellite applications is surveyed. Instructive examples are collected that demonstrate shortcomings of our intuition while dealing with complex systems and parameter interactions. We ponder over the scientific and business opportunities of new promising techniques and prospective applications.","PeriodicalId":208195,"journal":{"name":"Optical Microlithography XXXII","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123466685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Conley, Yaobin Feng, Zhiyang Song, Moran Guo, Junhao He, Longxia Guo, Gang Xu, S. Hsieh, J. Bonafede, S. Hsu, Austin Peng, Junwei Lu, Victor Peng, Beeri Nativ, Fei Jia, H. Nicolai, Ijen van Mil
All chipmakers understand that variability is the adversary of any process and reduction is essential to improving yield which translates to profit. Aggressive process window and yield specifications necessitate tight inline variation requirements on the DUV light source which impact scanner imaging performance. Improvements in reducing bandwidth variation have been realized with DynaPulse™ bandwidth control technology as significant reduction in bandwidth variation translates to a reduction in CD variation for critical device structures. Previous work on a NAND Via layer has demonstrated an improvement in process capability through improve source and mask optimization with greater ILS and reduced MEEF that improved CDU by 25%. Using this Via layer, we have developed a methodology to quantify the contribution in an overall CDU budget breakdown. Data from the light source is collected using SmartPulse™ allowing for the development of additional methodologies using predictive models to quantify CD variation from Cymer’s legacy, DynaPulse 1 and DynaPulse 2 bandwidth control technologies. CD non-uniformities due to laser bandwidth variation for lot to lot, wafer to wafer, field to field and within field is now available based on known sensitivities and modeled. This data can assist in understanding the contribution from laser bandwidth variation in global and local CDU budgets.
{"title":"Quantifying global and local CD variation for an advanced 3D NAND layer (Conference Presentation)","authors":"W. Conley, Yaobin Feng, Zhiyang Song, Moran Guo, Junhao He, Longxia Guo, Gang Xu, S. Hsieh, J. Bonafede, S. Hsu, Austin Peng, Junwei Lu, Victor Peng, Beeri Nativ, Fei Jia, H. Nicolai, Ijen van Mil","doi":"10.1117/12.2515725","DOIUrl":"https://doi.org/10.1117/12.2515725","url":null,"abstract":"All chipmakers understand that variability is the adversary of any process and reduction is essential to improving yield which translates to profit. Aggressive process window and yield specifications necessitate tight inline variation requirements on the DUV light source which impact scanner imaging performance. Improvements in reducing bandwidth variation have been realized with DynaPulse™ bandwidth control technology as significant reduction in bandwidth variation translates to a reduction in CD variation for critical device structures.\u0000\u0000Previous work on a NAND Via layer has demonstrated an improvement in process capability through improve source and mask optimization with greater ILS and reduced MEEF that improved CDU by 25%. Using this Via layer, we have developed a methodology to quantify the contribution in an overall CDU budget breakdown. Data from the light source is collected using SmartPulse™ allowing for the development of additional methodologies using predictive models to quantify CD variation from Cymer’s legacy, DynaPulse 1 and DynaPulse 2 bandwidth control technologies. CD non-uniformities due to laser bandwidth variation for lot to lot, wafer to wafer, field to field and within field is now available based on known sensitivities and modeled. This data can assist in understanding the contribution from laser bandwidth variation in global and local CDU budgets.","PeriodicalId":208195,"journal":{"name":"Optical Microlithography XXXII","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126358756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Oga, T. Yamazaki, T. Ohta, H. Tsushima, Satoru Bushida
Latest ArF immersion lithography has been positioned as the promising technology to meet tighter process control requirements with providing highly efficient productivity, simultaneously. The most important features for the next generation lightsources are the improvement of chip yield and tool availability in manufacturing. One of the key requirements for lightsource is E95% bandwidth, which has become more critical parameter for enhancing process margin and improving optical characteristic. Lower E95% bandwidth enables to increase imaging contrast which demonstrates better OPE characteristic with better resolution as well as improved E95% bandwidth stability that providing CD uniformity on wafer. A newly designed line narrowing module (LNM) enables to lower E95% bandwidth from the standard 300fm to 200fm. The large shrinkage for E95% bandwidth is achieved by the sophisticated design in LNM which enables to lower thermal wave front aberration reducing heat effect at optical elements and mechanical components during lasing the lights. Lower E95% bandwidth reduces a focus blur in the formulated image that is generated from the chromatic aberration with projection lenses in ArF immersion lithography system. In the other hand, it is essential to improve the productivity by means of reducing downtime, the lifetime of consumable modules such as a chamber and a line narrowing module (LNM) is needed to be extended. New electrodes as called “RAIKIRI” electrode with chamber enable lifetime extension from 60 billion pulses (Bpls) to 80 Bpls. Furthermore, new optical design in LNM enables the lifetime to extend from 60 Bpls to 110 Bpls. Hence, the GT65A, maximizes device yield, process productivity therefore provides optimum in the operational costs for chipmakers. In the presentation, the latest development status and performances on GT65A will be discussed.
{"title":"Next generation ArF lightsource \"T65A\" for cutting-edge immersion lithography providing both high in productivity and performance (Conference Presentation)","authors":"T. Oga, T. Yamazaki, T. Ohta, H. Tsushima, Satoru Bushida","doi":"10.1117/12.2515653","DOIUrl":"https://doi.org/10.1117/12.2515653","url":null,"abstract":"Latest ArF immersion lithography has been positioned as the promising technology to meet tighter process control requirements with providing highly efficient productivity, simultaneously. The most important features for the next generation lightsources are the improvement of chip yield and tool availability in manufacturing. One of the key requirements for lightsource is E95% bandwidth, which has become more critical parameter for enhancing process margin and improving optical characteristic. Lower E95% bandwidth enables to increase imaging contrast which demonstrates better OPE characteristic with better resolution as well as improved E95% bandwidth stability that providing CD uniformity on wafer. A newly designed line narrowing module (LNM) enables to lower E95% bandwidth from the standard 300fm to 200fm. The large shrinkage for E95% bandwidth is achieved by the sophisticated design in LNM which enables to lower thermal wave front aberration reducing heat effect at optical elements and mechanical components during lasing the lights. Lower E95% bandwidth reduces a focus blur in the formulated image that is generated from the chromatic aberration with projection lenses in ArF immersion lithography system. In the other hand, it is essential to improve the productivity by means of reducing downtime, the lifetime of consumable modules such as a chamber and a line narrowing module (LNM) is needed to be extended. New electrodes as called “RAIKIRI” electrode with chamber enable lifetime extension from 60 billion pulses (Bpls) to 80 Bpls. Furthermore, new optical design in LNM enables the lifetime to extend from 60 Bpls to 110 Bpls. Hence, the GT65A, maximizes device yield, process productivity therefore provides optimum in the operational costs for chipmakers.\u0000 In the presentation, the latest development status and performances on GT65A will be discussed.","PeriodicalId":208195,"journal":{"name":"Optical Microlithography XXXII","volume":"3 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114145989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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