Pub Date : 2009-06-15DOI: 10.1109/ESTC.2012.6542089
R. Windemuth, Takatoshi Ishikawa
Flipchip Technology is getting more and more important for future packaging solutions. This presentation gives an overview of different Flipchip Technology Solutions provided by industry. Mainstream Technologies such as C4 and ACF / ACP processes are explained. In special focus will be recently developed new processes to improve: Thermosonic Gold to Gold Interconnect (GGI) Process and Encapsulant Solder Connect (ESC) Process. Those being very fast and highly reliable. This is why they are suitable for further future miniturization. They cover a wide range of industrie´s product applications. Typical characteristics and process parameters for ESC and GGI will be described and analysed. Reliability data will be shown and explained. Both processes are suitable to be used in Chip on Board (COB), Waferlevel (COW) and Embedded Packaging Technology & Assembly. Some examples of how to use Flipchip processes for embedding active components to FR4 Printed Circuit boards (PCB) are shown and explained.
{"title":"New flipchip technology","authors":"R. Windemuth, Takatoshi Ishikawa","doi":"10.1109/ESTC.2012.6542089","DOIUrl":"https://doi.org/10.1109/ESTC.2012.6542089","url":null,"abstract":"Flipchip Technology is getting more and more important for future packaging solutions. This presentation gives an overview of different Flipchip Technology Solutions provided by industry. Mainstream Technologies such as C4 and ACF / ACP processes are explained. In special focus will be recently developed new processes to improve: Thermosonic Gold to Gold Interconnect (GGI) Process and Encapsulant Solder Connect (ESC) Process. Those being very fast and highly reliable. This is why they are suitable for further future miniturization. They cover a wide range of industrie´s product applications. Typical characteristics and process parameters for ESC and GGI will be described and analysed. Reliability data will be shown and explained. Both processes are suitable to be used in Chip on Board (COB), Waferlevel (COW) and Embedded Packaging Technology & Assembly. Some examples of how to use Flipchip processes for embedding active components to FR4 Printed Circuit boards (PCB) are shown and explained.","PeriodicalId":275745,"journal":{"name":"2009 European Microelectronics and Packaging Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121592636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-06-15DOI: 10.1109/EPTC.2009.5416414
TH Eric Kuah, J. Hao, J. Ding, Qf Li, W. Chan, S. Ho, HM Huang, Yj Jiang
The interest of user for WLP has been raised because of benefits such as reduced package thickness, fan-out capability, high I/O, substrate-less process, integration of passives into structure, good thermal and electrical performance. The objective of this paper is to delineate technical challenges and issues that potential adopter of wafer level molding will face, technological solution availability and the broad application of WLP using granulated epoxy and liquid encapsulant such as epoxy, hybrid of epoxy-silicone, silicone. Result base on actual molding trial indicates among the different form of wafer level molding the challenges being faced are similar, including co-planarity, warpage, die shifting, coefficient of thermal expansion matching, incomplete filling, MBF and voiding
{"title":"Encapsulation challenges for wafer level packaging","authors":"TH Eric Kuah, J. Hao, J. Ding, Qf Li, W. Chan, S. Ho, HM Huang, Yj Jiang","doi":"10.1109/EPTC.2009.5416414","DOIUrl":"https://doi.org/10.1109/EPTC.2009.5416414","url":null,"abstract":"The interest of user for WLP has been raised because of benefits such as reduced package thickness, fan-out capability, high I/O, substrate-less process, integration of passives into structure, good thermal and electrical performance. The objective of this paper is to delineate technical challenges and issues that potential adopter of wafer level molding will face, technological solution availability and the broad application of WLP using granulated epoxy and liquid encapsulant such as epoxy, hybrid of epoxy-silicone, silicone. Result base on actual molding trial indicates among the different form of wafer level molding the challenges being faced are similar, including co-planarity, warpage, die shifting, coefficient of thermal expansion matching, incomplete filling, MBF and voiding","PeriodicalId":275745,"journal":{"name":"2009 European Microelectronics and Packaging Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123175458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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