Pub Date : 2022-02-04DOI: 10.1007/s10776-022-00551-0
B. Ghosh, A. Chandra, A. K. Mal
{"title":"Fuzzy Logic-Based Energy-Optimal Collinear DF Relay Placement in Two-Hop η -μ Fading Channel","authors":"B. Ghosh, A. Chandra, A. K. Mal","doi":"10.1007/s10776-022-00551-0","DOIUrl":"https://doi.org/10.1007/s10776-022-00551-0","url":null,"abstract":"","PeriodicalId":277550,"journal":{"name":"Int. J. Wirel. Inf. Networks","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129367308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-01DOI: 10.1504/ijstm.2020.10029154
Aastha Modgil, V. Sehgal, Nitin Chanderwal
In a chip multiprocessor (CMP) major resource that is being shared among multiple cores is main memory as it is responsible for storing data structures needed for execution of a program. Diverse threads running simultaneously on same chip may compete with each other for resources. Because of interference among threads, each thread can experience extremely different memory system performance. If interference among threads is not controlled, then one thread can experience extreme slowdown while another is unfairly prioritised. By efficiently reordering concurrent memory requests, power consumption and thread fairness can be improved. This work proposes a memory access scheduler, energy-efficient fairness-aware (EEFA) memory access scheduling that provides thread fairness, exploits bank level parallelism by pre-issuing issuable read commands during drain-write mode. Also, proposed scheduler prioritises row buffer hit requests. The authors show that EEFA memory access scheduling significantly reduces unfairness among threads and energy consumption in DRAM memory system while also improving performance.
{"title":"Energy-efficient fairness-aware memory access scheduling","authors":"Aastha Modgil, V. Sehgal, Nitin Chanderwal","doi":"10.1504/ijstm.2020.10029154","DOIUrl":"https://doi.org/10.1504/ijstm.2020.10029154","url":null,"abstract":"In a chip multiprocessor (CMP) major resource that is being shared among multiple cores is main memory as it is responsible for storing data structures needed for execution of a program. Diverse threads running simultaneously on same chip may compete with each other for resources. Because of interference among threads, each thread can experience extremely different memory system performance. If interference among threads is not controlled, then one thread can experience extreme slowdown while another is unfairly prioritised. By efficiently reordering concurrent memory requests, power consumption and thread fairness can be improved. This work proposes a memory access scheduler, energy-efficient fairness-aware (EEFA) memory access scheduling that provides thread fairness, exploits bank level parallelism by pre-issuing issuable read commands during drain-write mode. Also, proposed scheduler prioritises row buffer hit requests. The authors show that EEFA memory access scheduling significantly reduces unfairness among threads and energy consumption in DRAM memory system while also improving performance.","PeriodicalId":277550,"journal":{"name":"Int. J. Wirel. Inf. Networks","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125076454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1504/ijstm.2020.10029156
Fu Huang, Huaming Song
{"title":"Periodic review integrated inventory model with controllable lead time and setup cost in the presence of a service level constraint","authors":"Fu Huang, Huaming Song","doi":"10.1504/ijstm.2020.10029156","DOIUrl":"https://doi.org/10.1504/ijstm.2020.10029156","url":null,"abstract":"","PeriodicalId":277550,"journal":{"name":"Int. J. Wirel. Inf. Networks","volume":"121 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132767906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1504/ijstm.2020.10029155
Rafael Teixeira, E. Paiva, C. Matos, P. Vesel
{"title":"The joint effect of buyer-supplier interaction and service complexity on B2B buyer satisfaction","authors":"Rafael Teixeira, E. Paiva, C. Matos, P. Vesel","doi":"10.1504/ijstm.2020.10029155","DOIUrl":"https://doi.org/10.1504/ijstm.2020.10029155","url":null,"abstract":"","PeriodicalId":277550,"journal":{"name":"Int. J. Wirel. Inf. Networks","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115410870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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