Bytecode hardware-translation improves the performance of a Java Virtual Machine (JVM) with small hardware resource and complexity overhead. Instruction folding is a technique to further improve the performance of a JVM by reducing the redundancy in the stack-based instruction execution. However, the variable instruction length of the Java bytecode makes the folding logic complex. In this paper, we propose a folding scheme with reduced hardware complexity and evaluate its performance. For seven benchmark cases, the proposed scheme folded 6.6% to 37.1% of the bytecodes which correspond to 84.2% to 102% of the PicoJava-II's performance.
{"title":"Instruction folding in a hardware-translation based java virtual machine","authors":"Hitoshi Oi","doi":"10.1145/1128022.1128041","DOIUrl":"https://doi.org/10.1145/1128022.1128041","url":null,"abstract":"Bytecode hardware-translation improves the performance of a Java Virtual Machine (JVM) with small hardware resource and complexity overhead. Instruction folding is a technique to further improve the performance of a JVM by reducing the redundancy in the stack-based instruction execution. However, the variable instruction length of the Java bytecode makes the folding logic complex. In this paper, we propose a folding scheme with reduced hardware complexity and evaluate its performance. For seven benchmark cases, the proposed scheme folded 6.6% to 37.1% of the bytecodes which correspond to 84.2% to 102% of the PicoJava-II's performance.","PeriodicalId":278223,"journal":{"name":"J. Instr. Level Parallelism","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124167799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.5325/jnietstud.42.1.0004
Alaa R. Alameldeen
This special issue consists of extended papers from the First Data Prefetching Championship (DPC-1). Earlier versions of these papers were published at a workshop held in conjunction with the 15 th Annual International Conference on High-Performance Computer Architecture (HPCA15) in Raleigh, NC, in February 2009. I invited authors from the workshop to extend their papers for this special issue of JILP.
{"title":"Guest Editor's Introduction","authors":"Alaa R. Alameldeen","doi":"10.5325/jnietstud.42.1.0004","DOIUrl":"https://doi.org/10.5325/jnietstud.42.1.0004","url":null,"abstract":"This special issue consists of extended papers from the First Data Prefetching Championship (DPC-1). Earlier versions of these papers were published at a workshop held in conjunction with the 15 th Annual International Conference on High-Performance Computer Architecture (HPCA15) in Raleigh, NC, in February 2009. I invited authors from the workshop to extend their papers for this special issue of JILP.","PeriodicalId":278223,"journal":{"name":"J. Instr. Level Parallelism","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124618335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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