Pub Date : 2021-08-09DOI: 10.5772/intechopen.96085
A. E. Abejide, Madhava Reddy Kota, Sushma Pandey, O. Aboderin, Cátia Pinho, M. Lima, A. Teixeira
The demand for low-cost high-speed transmission is a major challenge for 5G future networks. To meet this optical communication demand, holistic and painstaking approaches are required in designing a simplified system model. Since the demands for high bandwidth are growing at unprecedented speed as we approach the Zettabyte era, it is crucial to minimize chromatic dispersion (CD) associated to high bit-rate signals. Mitigating CD electronically comes at high cost which may not be compatible with 5G. Photonic Integrated Circuit (PIC) as an enabler for fast speed optical transmission is still undergoing its growth stage and its major speed and efficiency have not yet been attained. However, proper and right combination of components and approaches can potentiate this technology in a more cost-efficient way. Hybrid modulation (HM)-PIC presents a simplified approach in terms of cost and efficiency for 5G networks. Hybridization of existing modulation components and approaches in PIC can enhance the generation of high bit-rate signals without the need for electrical CD compensation. A detailed study of hybrid multilevel signal modulation concept as a valuable solution for Data Centers (DC) high data-rate signals and next-generation Passive Optical Networks (PONs) is proposed.
{"title":"Direct and External Hybrid Modulation Approaches for Access Networks","authors":"A. E. Abejide, Madhava Reddy Kota, Sushma Pandey, O. Aboderin, Cátia Pinho, M. Lima, A. Teixeira","doi":"10.5772/intechopen.96085","DOIUrl":"https://doi.org/10.5772/intechopen.96085","url":null,"abstract":"The demand for low-cost high-speed transmission is a major challenge for 5G future networks. To meet this optical communication demand, holistic and painstaking approaches are required in designing a simplified system model. Since the demands for high bandwidth are growing at unprecedented speed as we approach the Zettabyte era, it is crucial to minimize chromatic dispersion (CD) associated to high bit-rate signals. Mitigating CD electronically comes at high cost which may not be compatible with 5G. Photonic Integrated Circuit (PIC) as an enabler for fast speed optical transmission is still undergoing its growth stage and its major speed and efficiency have not yet been attained. However, proper and right combination of components and approaches can potentiate this technology in a more cost-efficient way. Hybrid modulation (HM)-PIC presents a simplified approach in terms of cost and efficiency for 5G networks. Hybridization of existing modulation components and approaches in PIC can enhance the generation of high bit-rate signals without the need for electrical CD compensation. A detailed study of hybrid multilevel signal modulation concept as a valuable solution for Data Centers (DC) high data-rate signals and next-generation Passive Optical Networks (PONs) is proposed.","PeriodicalId":296286,"journal":{"name":"Network-on-Chip [Working Title]","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116606103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-25DOI: 10.5772/intechopen.97341
Riko Herwanto, Nurfiana
The modules on the IC unit now and then semiconductor science centers schematizing fluctuated elements of the PC framework and unit intended to be ordinary among the feeling of organization science. Another issue in NoC environmental factors is that the directing recipe. Regarding conveying system, for example alteration strategy, their unit contrasting sorts of adjustment strategies like circuit change, bundle alteration, and empty adjustment. The configurable interconnection parts give a data profitable, significantly progressed association from the processor and information perilous in place based knowledge official structures. What’s extra, the configurable Interconnect supports a multi-layer topography that guarantees the fundamental plan of assessment and low torpidity for each related Ip and it gives related advancements, as for voltage and repeat scaling. The Open Core Protocol can be a fitting and play interface for a middle having every master and slave interfaces. Organization interfacing: The achievement of the NoC style worldview relies significantly upon the normalization of the interfaces between science centers and furthermore the interconnection material. As demonstrated inside the figure beneath, for a center having each expert and slave interfaces, the OCP agreeable signs of the deliberate science block square measure packetized by a subsequent interface.
{"title":"Design and Optimization of Networks-on-Chip","authors":"Riko Herwanto, Nurfiana","doi":"10.5772/intechopen.97341","DOIUrl":"https://doi.org/10.5772/intechopen.97341","url":null,"abstract":"The modules on the IC unit now and then semiconductor science centers schematizing fluctuated elements of the PC framework and unit intended to be ordinary among the feeling of organization science. Another issue in NoC environmental factors is that the directing recipe. Regarding conveying system, for example alteration strategy, their unit contrasting sorts of adjustment strategies like circuit change, bundle alteration, and empty adjustment. The configurable interconnection parts give a data profitable, significantly progressed association from the processor and information perilous in place based knowledge official structures. What’s extra, the configurable Interconnect supports a multi-layer topography that guarantees the fundamental plan of assessment and low torpidity for each related Ip and it gives related advancements, as for voltage and repeat scaling. The Open Core Protocol can be a fitting and play interface for a middle having every master and slave interfaces. Organization interfacing: The achievement of the NoC style worldview relies significantly upon the normalization of the interfaces between science centers and furthermore the interconnection material. As demonstrated inside the figure beneath, for a center having each expert and slave interfaces, the OCP agreeable signs of the deliberate science block square measure packetized by a subsequent interface.","PeriodicalId":296286,"journal":{"name":"Network-on-Chip [Working Title]","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114412656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-04-13DOI: 10.5772/INTECHOPEN.97262
I. Alimi, Romil K. Patel, O. Aboderin, Abdelgader M. Abdalla, Ramoni A. Gbadamosi, N. Muga, A. Pinto, A. Teixeira
Integration technology advancement has impacted the System-on-Chip (SoC) in which heterogeneous cores are supported on a single chip. Based on the huge amount of supported heterogeneous cores, efficient communication between the associated processors has to be considered at all levels of the system design to ensure global interconnection. This can be achieved through a design-friendly, flexible, scalable, and high-performance interconnection architecture. It is noteworthy that the interconnections between multiple cores on a chip present a considerable influence on the performance and communication of the chip design regarding the throughput, end-to-end delay, and packets loss ratio. Although hierarchical architectures have addressed the majority of the associated challenges of the traditional interconnection techniques, the main limiting factor is scalability. Network-on-Chip (NoC) has been presented as a scalable and well-structured alternative solution that is capable of addressing communication issues in the on-chip systems. In this context, several NoC topologies have been presented to support various routing techniques and attend to different chip architectural requirements. This book chapter reviews some of the existing NoC topologies and their associated characteristics. Also, application mapping algorithms and some key challenges of NoC are considered.
{"title":"Network-On-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction","authors":"I. Alimi, Romil K. Patel, O. Aboderin, Abdelgader M. Abdalla, Ramoni A. Gbadamosi, N. Muga, A. Pinto, A. Teixeira","doi":"10.5772/INTECHOPEN.97262","DOIUrl":"https://doi.org/10.5772/INTECHOPEN.97262","url":null,"abstract":"Integration technology advancement has impacted the System-on-Chip (SoC) in which heterogeneous cores are supported on a single chip. Based on the huge amount of supported heterogeneous cores, efficient communication between the associated processors has to be considered at all levels of the system design to ensure global interconnection. This can be achieved through a design-friendly, flexible, scalable, and high-performance interconnection architecture. It is noteworthy that the interconnections between multiple cores on a chip present a considerable influence on the performance and communication of the chip design regarding the throughput, end-to-end delay, and packets loss ratio. Although hierarchical architectures have addressed the majority of the associated challenges of the traditional interconnection techniques, the main limiting factor is scalability. Network-on-Chip (NoC) has been presented as a scalable and well-structured alternative solution that is capable of addressing communication issues in the on-chip systems. In this context, several NoC topologies have been presented to support various routing techniques and attend to different chip architectural requirements. This book chapter reviews some of the existing NoC topologies and their associated characteristics. Also, application mapping algorithms and some key challenges of NoC are considered.","PeriodicalId":296286,"journal":{"name":"Network-on-Chip [Working Title]","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133278758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-03-23DOI: 10.5772/INTECHOPEN.95075
E. Sakthivel, R. Madavan
A real-time multiprocessor chip model is also called a Network-on-Chip (NoC), and deals a promising architecture for future systems-on-chips. Even though a lot of Double Tail Sense Amplifiers are used in architectural approach, the existing DTSA with transceiver exhibits a difficulty of consuming more energy than its gouged design during various traffic condition. Novel Low Power pulse Triggered Flip Flop with DTSA is designed in this research to eliminate the difficulty. The Traffic Aware Sense amplifier MAS consists of Sense amplifiers (SA’s), Traffic Generator, and Estimator. Among various SA’S suitable (DTSA and NLPTF -DTSA) SA are selected and information transferred to the receiver. The performance of both DTSA with Transceiver and NLPTF-DTSA with transceiver compared under various traffic conditions. The proposed design (NLPTF-DTSA) is observed on TSMC 90 nm technology, showing 5.92 Gb/s data rate and 0.51 W total link power.
{"title":"MAS: Maximum Energy-Aware Sense Amplifier Link for Asynchronous Network on Chip","authors":"E. Sakthivel, R. Madavan","doi":"10.5772/INTECHOPEN.95075","DOIUrl":"https://doi.org/10.5772/INTECHOPEN.95075","url":null,"abstract":"A real-time multiprocessor chip model is also called a Network-on-Chip (NoC), and deals a promising architecture for future systems-on-chips. Even though a lot of Double Tail Sense Amplifiers are used in architectural approach, the existing DTSA with transceiver exhibits a difficulty of consuming more energy than its gouged design during various traffic condition. Novel Low Power pulse Triggered Flip Flop with DTSA is designed in this research to eliminate the difficulty. The Traffic Aware Sense amplifier MAS consists of Sense amplifiers (SA’s), Traffic Generator, and Estimator. Among various SA’S suitable (DTSA and NLPTF -DTSA) SA are selected and information transferred to the receiver. The performance of both DTSA with Transceiver and NLPTF-DTSA with transceiver compared under various traffic conditions. The proposed design (NLPTF-DTSA) is observed on TSMC 90 nm technology, showing 5.92 Gb/s data rate and 0.51 W total link power.","PeriodicalId":296286,"journal":{"name":"Network-on-Chip [Working Title]","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130992427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：