Pub Date : 2015-05-08DOI: 10.1515/BPASTS-2016-0091
A. Gramacki, Marek Sawerwain, J. Gramacki
FPGA technology can offer significantly hi-gher performance at much lower power consumption than is available from CPUs and GPUs in many computational problems. Unfortunately, programming for FPGA (using ha-rdware description languages, HDL) is a difficult and not-trivial task and is not intuitive for C/C++/Java programmers. To bring the gap between programming effectiveness and difficulty the High Level Synthesis (HLS) approach is promoting by main FPGA vendors. Nowadays, time-intensive calculations are mainly performed on GPU/CPU architectures, but can also be successfully performed using HLS approach. In the paper we implement a bandwidth selection algorithm for kernel density estimation (KDE) using HLS and show techniques which were used to optimize the final FPGA implementation. We are also going to show that FPGA speedups, comparing to highly optimized CPU and GPU implementations, are quite substantial. Moreover, power consumption for FPGA devices is usually much less than typical power consumption of the present CPUs and GPUs.
在许多计算问题中，FPGA技术可以以比cpu和gpu低得多的功耗提供显著更高的性能。不幸的是，为FPGA编程(使用ha硬件描述语言，HDL)是一项困难且不平凡的任务，对于C/ c++ /Java程序员来说并不直观。为了消除编程效率和编程难度之间的差距，各大FPGA厂商都在推广高级综合(High Level Synthesis, HLS)方法。目前，时间密集型计算主要在GPU/CPU架构上执行，但也可以使用HLS方法成功执行。在本文中，我们使用HLS和show技术实现了一种用于核密度估计(KDE)的带宽选择算法，该算法用于优化最终的FPGA实现。我们还将展示，与高度优化的CPU和GPU实现相比，FPGA的加速是相当可观的。此外，FPGA器件的功耗通常比当前cpu和gpu的典型功耗低得多。
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Pub Date : 2014-04-15DOI: 10.14445/22312803/IJCTT-V9150
Richa Gupta, Sunny Gupta, Anuradha Singhal
Big data is data that exceeds the processing capacity of traditional databases. The data is too big to be processed by a single machine. New and innovative methods are required to process and store such large volumes of data. This paper provides an overview on big data, its importance in our live and some technologies to handle big data.
{"title":"Big Data: Overview","authors":"Richa Gupta, Sunny Gupta, Anuradha Singhal","doi":"10.14445/22312803/IJCTT-V9150","DOIUrl":"https://doi.org/10.14445/22312803/IJCTT-V9150","url":null,"abstract":"Big data is data that exceeds the processing capacity of traditional databases. The data is too big to be processed by a single machine. New and innovative methods are required to process and store such large volumes of data. This paper provides an overview on big data, its importance in our live and some technologies to handle big data.","PeriodicalId":298801,"journal":{"name":"arXiv: Other Computer Science","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132047733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.5121/IJWEST.2013.4406
R. Chamoun
A mashup is a combination of information from more than one source, mixed up in a way to create something new, or at least useful. Anyone can find mashups on the internet, but these are always specifically designed for a predefined purpose. To change that fact, we implemented a new platform we called the SMART platform. SMART enables the user to make his own choices as for the REST web services he needs to call in order to build an intelligent personalized mashup, from a Google-like simple search interface, without needing any programming skills. In order to achieve this goal, we defined an ontology that can hold REST web services descriptions. These descriptions encapsulate mainly, the input type needed for a service, its output type, and the kind of relation that ties the input to the output. Then, by matching the user input query keywords, with the REST web services definitions in our ontology, we can find registered services individuals in this ontology, and construct the raw REST query for each service found. The wrap up from the keywords, into semantic definitions, in order to find the matching service individual, then the wrap down from the semantic service description of the found individual, to the raw REST call, and finally the wrap up of the result again into semantic individuals, is done for two main purposes: the first to let the user use simple keywords in order to build complex mashups, and the second to benefit from the ontology inference engine in a way, where services instances can be tied together into an intelligent mashup, simply by making each service output individuals, stand as the next service input.
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A. Sinha, Soumojit Acharyya, Suranjan Chakraborty, Mitrava Sarkar
Digital Signal Processing functions are widely used in real time high speed applications. Those functions are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively smaller utilization factor or lower speed compared to ASIC. The proposed reconfigurable DSP processor is redolent to FPGA, but with basic fixed Common Modules (CMs) (like adders, subtractors, multipliers, scaling units, shifters) instead of CLBs. This paper introduces the development of a reconfigurable DSP processor that integrates different filter and transform functions. The switching between DSP functions is occurred by reconfiguring the interconnection between CMs. Validation of the proposed reconfigurable architecture has been achieved on Virtex5 FPGA. The architecture provides sufficient amount of flexibility, parallelism and scalability.
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Pub Date : 2008-01-15DOI: 10.1002/9780470050118.ecse316
I. Damaj
Programmable logic arrays (PLAs) are traditional digital electronic devices. A PLA is a simple programmable logic device (SPLD) used to implement combinational logic circuits. A PLA has a set of programmable AND gates, which link to a set of programmable OR gates to produce an output. The AND–OR layout of a PLA allows for implementing logic functions that are in a sum-of-products form. PLAs are available in the market in different types. PLAs could be stand alone chips, or parts of bigger processing systems. Stand alone PLAs are available as mask programmable (MPLAs) and field programmable (FPLAs) devices. The attractions of PLAs that brought them to mainstream engineers include their simplicity, relatively small circuit area, predictable propagation delay, and ease of development. The powerful-but-simple property brought PLAs to rapid prototyping, synthesis, design optimization techniques, embedded systems, traditional computer systems, hybrid high-performance computing systems, etc. Indeed, there has been renewable interests in working with the simple AND-to-OR PLAs. Keywords: gate arrays; programmable logic; logic design; digital systems; boolean algebra; digital electronics; rapid prototyping; hardware synthesis
{"title":"Programmable Logic Arrays","authors":"I. Damaj","doi":"10.1002/9780470050118.ecse316","DOIUrl":"https://doi.org/10.1002/9780470050118.ecse316","url":null,"abstract":"Programmable logic arrays (PLAs) are traditional digital electronic devices. A PLA is a simple programmable logic device (SPLD) used to implement combinational logic circuits. A PLA has a set of programmable AND gates, which link to a set of programmable OR gates to produce an output. The AND–OR layout of a PLA allows for implementing logic functions that are in a sum-of-products form. PLAs are available in the market in different types. PLAs could be stand alone chips, or parts of bigger processing systems. Stand alone PLAs are available as mask programmable (MPLAs) and field programmable (FPLAs) devices. The attractions of PLAs that brought them to mainstream engineers include their simplicity, relatively small circuit area, predictable propagation delay, and ease of development. The powerful-but-simple property brought PLAs to rapid prototyping, synthesis, design optimization techniques, embedded systems, traditional computer systems, hybrid high-performance computing systems, etc. Indeed, there has been renewable interests in working with the simple AND-to-OR PLAs. \u0000 \u0000 \u0000Keywords: \u0000 \u0000gate arrays; \u0000programmable logic; \u0000logic design; \u0000digital systems; \u0000boolean algebra; \u0000digital electronics; \u0000rapid prototyping; \u0000hardware synthesis","PeriodicalId":298801,"journal":{"name":"arXiv: Other Computer Science","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130366912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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