Pub Date : 2021-11-01DOI: 10.1109/eduhpc54835.2021.00011
H. Gabb, Alexandru Nicolau, S. Puri, Michael D. Shah, Rahul Toppur, Neftali Watkinson, Weijia Xu, Hui Zhang
The EduHPC lightning talks are an opportunity for educators to discuss early results. These talks are compiled into this paper. The EduHPC 2021 lightning talks cover diverse pedagogical topics in parallel and distributed computing: teaching instruction-level parallelism in the context of computer organization, parallelizing cipher algorithms using single-instruction multiple threads, teaching edge computing to undergraduates, and deploying education-as-a-service on HPC resources.
{"title":"Lightning Talks of EduHPC 2021","authors":"H. Gabb, Alexandru Nicolau, S. Puri, Michael D. Shah, Rahul Toppur, Neftali Watkinson, Weijia Xu, Hui Zhang","doi":"10.1109/eduhpc54835.2021.00011","DOIUrl":"https://doi.org/10.1109/eduhpc54835.2021.00011","url":null,"abstract":"The EduHPC lightning talks are an opportunity for educators to discuss early results. These talks are compiled into this paper. The EduHPC 2021 lightning talks cover diverse pedagogical topics in parallel and distributed computing: teaching instruction-level parallelism in the context of computer organization, parallelizing cipher algorithms using single-instruction multiple threads, teaching edge computing to undergraduates, and deploying education-as-a-service on HPC resources.","PeriodicalId":318900,"journal":{"name":"2021 IEEE/ACM Ninth Workshop on Education for High Performance Computing (EduHPC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128335945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-01DOI: 10.1109/eduhpc54835.2021.00008
E. Siegmann, A. Calder, Catherine Feldman, R. Harrison
We examine a multi-modal approach to educating and training users of an advanced computing technology testbed at the Institute for Advanced Computational Science at Stony Brook University. Ookami [1] provides researchers worldwide with access to 176 Fujitsu A64FX compute nodes, this being the same processor technology powering the Japanese Fugaku supercomputer, the fastest computer in the world since June 2020. However, achieving high-performance on this Arm-based, leadership computing technology requires that users be familiar with details of computer architecture, performance analysis and modeling, and high-performance programming models that are commonly omitted in introductory programming courses. Indeed, regardless of their seniority, many of the testbed users are surprisingly unfamiliar with basic concepts such as vectorization, pipelining, latency/bandwidth, roofline models, computing energy/power, threads, and non-uniform memory access. These same concepts also pervade mainstream x86 technologies, so this is of widespread concern. Due to the national/global nature of our user community that is also very diverse in both discipline and experience, the inability to offer formal classes, and our experience that most people do not tend to read online documentation or training materials in sufficient depth, we have consciously employed multiple approaches that heavily emphasize (online) personal interactions and transfer of skills. Online documentation has been organized around best-practices and FAQs; twice-weekly hackathons and office hours via Zoom enable deep dives by both the team and the user community with multiple broad benefits; a Slack channel provides both real time and archived answers and discussions; and workshops, training and webinars target community needs as they arise. The perspective that these tools are being used in an educational setting rather than just for project communication makes them more effective and contributes to community success.
{"title":"Educating HPC Users in the use of advanced computing technology","authors":"E. Siegmann, A. Calder, Catherine Feldman, R. Harrison","doi":"10.1109/eduhpc54835.2021.00008","DOIUrl":"https://doi.org/10.1109/eduhpc54835.2021.00008","url":null,"abstract":"We examine a multi-modal approach to educating and training users of an advanced computing technology testbed at the Institute for Advanced Computational Science at Stony Brook University. Ookami [1] provides researchers worldwide with access to 176 Fujitsu A64FX compute nodes, this being the same processor technology powering the Japanese Fugaku supercomputer, the fastest computer in the world since June 2020. However, achieving high-performance on this Arm-based, leadership computing technology requires that users be familiar with details of computer architecture, performance analysis and modeling, and high-performance programming models that are commonly omitted in introductory programming courses. Indeed, regardless of their seniority, many of the testbed users are surprisingly unfamiliar with basic concepts such as vectorization, pipelining, latency/bandwidth, roofline models, computing energy/power, threads, and non-uniform memory access. These same concepts also pervade mainstream x86 technologies, so this is of widespread concern. Due to the national/global nature of our user community that is also very diverse in both discipline and experience, the inability to offer formal classes, and our experience that most people do not tend to read online documentation or training materials in sufficient depth, we have consciously employed multiple approaches that heavily emphasize (online) personal interactions and transfer of skills. Online documentation has been organized around best-practices and FAQs; twice-weekly hackathons and office hours via Zoom enable deep dives by both the team and the user community with multiple broad benefits; a Slack channel provides both real time and archived answers and discussions; and workshops, training and webinars target community needs as they arise. The perspective that these tools are being used in an educational setting rather than just for project communication makes them more effective and contributes to community success.","PeriodicalId":318900,"journal":{"name":"2021 IEEE/ACM Ninth Workshop on Education for High Performance Computing (EduHPC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126201967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-01DOI: 10.1109/eduhpc54835.2021.00006
E. Frachtenberg
Heterogeneous computing is growing as an important hardware and software paradigm, both in high-performance computing and in application computing in general. Nevertheless, the topic is a relative newcomer to undergraduate curricula, and there is a dearth of guidance on suitable syllabi and lesson plans. The educational challenge of teaching this topic is exacerbated by the rapid pace of heterogeneous-hardware innovation and adoption, which can render parts of current textbooks obsolete.To help other educators facing these challenges, and to promote a conversation about a standardized approach toward teaching heterogeneous computing, this paper presents a case study for one semester-long class on the topic. It describes the goals, structure, challenges, and lessons learned from the introduction of a diverse heterogeneous hardware and software environment to computer science majors at Reed College, a small liberal-arts school. This paper also includes suggestions and ideas for future adoption, adaptation, and expansion of this class.
{"title":"Experience and Practice Teaching an Undergraduate Course on Diverse Heterogeneous Architectures","authors":"E. Frachtenberg","doi":"10.1109/eduhpc54835.2021.00006","DOIUrl":"https://doi.org/10.1109/eduhpc54835.2021.00006","url":null,"abstract":"Heterogeneous computing is growing as an important hardware and software paradigm, both in high-performance computing and in application computing in general. Nevertheless, the topic is a relative newcomer to undergraduate curricula, and there is a dearth of guidance on suitable syllabi and lesson plans. The educational challenge of teaching this topic is exacerbated by the rapid pace of heterogeneous-hardware innovation and adoption, which can render parts of current textbooks obsolete.To help other educators facing these challenges, and to promote a conversation about a standardized approach toward teaching heterogeneous computing, this paper presents a case study for one semester-long class on the topic. It describes the goals, structure, challenges, and lessons learned from the introduction of a diverse heterogeneous hardware and software environment to computer science majors at Reed College, a small liberal-arts school. This paper also includes suggestions and ideas for future adoption, adaptation, and expansion of this class.","PeriodicalId":318900,"journal":{"name":"2021 IEEE/ACM Ninth Workshop on Education for High Performance Computing (EduHPC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129808579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-01DOI: 10.1109/eduhpc54835.2021.00012
H. Casanova, Rafael Ferreira da Silva, Arturo González-Escribano, Herman Li, Yuri Torres, David P. Bunde
Peachy Parallel Assignments are high-quality assignments that are easy for other instructors to adopt and use in their own classes. They are selected competitively for presentation at the Edu* workshops based on ease of adoption and how "cool and inspirational" they are for students. The goals are to excite students about PDC, to save faculty the time and risk associated with creating new assignments, and to recognize faculty who create awesome assignments for their students.In this paper, we present two assignments. The first assignment is a simulation of air flow in a wind tunnel, which students parallelize using OpenMP, MPI, and CUDA to illustrate the different techniques needed for these paradigms. The second assignment is a series of exercises to teach students the principles of batch scheduling and how to interact with a batch scheduler to submit parallel jobs. It uses simulation to allow students to quickly see the results of their decisions and to support revisiting an earlier decision.
{"title":"Peachy Parallel Assignments (EduHPC 2021)","authors":"H. Casanova, Rafael Ferreira da Silva, Arturo González-Escribano, Herman Li, Yuri Torres, David P. Bunde","doi":"10.1109/eduhpc54835.2021.00012","DOIUrl":"https://doi.org/10.1109/eduhpc54835.2021.00012","url":null,"abstract":"Peachy Parallel Assignments are high-quality assignments that are easy for other instructors to adopt and use in their own classes. They are selected competitively for presentation at the Edu* workshops based on ease of adoption and how \"cool and inspirational\" they are for students. The goals are to excite students about PDC, to save faculty the time and risk associated with creating new assignments, and to recognize faculty who create awesome assignments for their students.In this paper, we present two assignments. The first assignment is a simulation of air flow in a wind tunnel, which students parallelize using OpenMP, MPI, and CUDA to illustrate the different techniques needed for these paradigms. The second assignment is a series of exercises to teach students the principles of batch scheduling and how to interact with a batch scheduler to submit parallel jobs. It uses simulation to allow students to quickly see the results of their decisions and to support revisiting an earlier decision.","PeriodicalId":318900,"journal":{"name":"2021 IEEE/ACM Ninth Workshop on Education for High Performance Computing (EduHPC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130196196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-01DOI: 10.1109/eduhpc54835.2021.00009
Grey Ballard, S. Parsons
The design and analysis of parallel algorithms are both fundamental to the set of high-performance, parallel, and distributed computing skills required to use modern computing resources efficiently. In this work, we present an approach of teaching parallel computing within an undergraduate algorithms course that combines the paradigms of dynamic programming and multithreaded parallelization. We have developed a visualization tool built with the Thread Safe Graphics Library that enables interactive demonstration of parallelization techniques for two fundamental dynamic programming problems, 0/1 Knapsack and Longest Common Subsequence. We describe the implementation of the tool, the real-time animation it produces, and the results of using it in class. The tool is publicly available to be used directly or as a basis on which to build visualizations of other parallel dynamic programming algorithms.
{"title":"Visualizing Parallel Dynamic Programming using the Thread Safe Graphics Library","authors":"Grey Ballard, S. Parsons","doi":"10.1109/eduhpc54835.2021.00009","DOIUrl":"https://doi.org/10.1109/eduhpc54835.2021.00009","url":null,"abstract":"The design and analysis of parallel algorithms are both fundamental to the set of high-performance, parallel, and distributed computing skills required to use modern computing resources efficiently. In this work, we present an approach of teaching parallel computing within an undergraduate algorithms course that combines the paradigms of dynamic programming and multithreaded parallelization. We have developed a visualization tool built with the Thread Safe Graphics Library that enables interactive demonstration of parallelization techniques for two fundamental dynamic programming problems, 0/1 Knapsack and Longest Common Subsequence. We describe the implementation of the tool, the real-time animation it produces, and the results of using it in class. The tool is publicly available to be used directly or as a basis on which to build visualizations of other parallel dynamic programming algorithms.","PeriodicalId":318900,"journal":{"name":"2021 IEEE/ACM Ninth Workshop on Education for High Performance Computing (EduHPC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131006480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-01DOI: 10.1109/eduhpc54835.2021.00010
P. Dewan, Andrew Wortas, Zhizhou Liu, Samuel George, Bowen Gu, Hao Wang
Existing techniques for automating the testing of sequential programming assignments are fundamentally at odds with concurrent programming as they are oblivious to the algorithm used to implement the assignments. We have developed a framework that addresses this limitation for those object-based concurrent assignments whose user-interface (a) is implemented using the observer pattern and (b) makes apparent whether concurrency requirements are met. It has two components. The first component reduces the number of steps a human grader needs to take to interact with and score the user-interfaces of the submitted programs. The second component completely automates assessment by observing the events sent by the student-implemented observable objects. Both components are used to score the final submission and log interaction. The second component is also used to provide feedback during assignment implementation. Our experience shows that the framework is used extensively by students, leads to more partial credit, reduces grading time, and gives statistics about incremental student progress.
{"title":"Automating Testing of Visual Observed Concurrency","authors":"P. Dewan, Andrew Wortas, Zhizhou Liu, Samuel George, Bowen Gu, Hao Wang","doi":"10.1109/eduhpc54835.2021.00010","DOIUrl":"https://doi.org/10.1109/eduhpc54835.2021.00010","url":null,"abstract":"Existing techniques for automating the testing of sequential programming assignments are fundamentally at odds with concurrent programming as they are oblivious to the algorithm used to implement the assignments. We have developed a framework that addresses this limitation for those object-based concurrent assignments whose user-interface (a) is implemented using the observer pattern and (b) makes apparent whether concurrency requirements are met. It has two components. The first component reduces the number of steps a human grader needs to take to interact with and score the user-interfaces of the submitted programs. The second component completely automates assessment by observing the events sent by the student-implemented observable objects. Both components are used to score the final submission and log interaction. The second component is also used to provide feedback during assignment implementation. Our experience shows that the framework is used extensively by students, leads to more partial credit, reduces grading time, and gives statistics about incremental student progress.","PeriodicalId":318900,"journal":{"name":"2021 IEEE/ACM Ninth Workshop on Education for High Performance Computing (EduHPC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131561510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-01DOI: 10.1109/eduhpc54835.2021.00007
Eric Shook, F. Bowlick, Anand Padmanabhan, Karen K. Kemp
This paper provides an overview of the Hour of Cyberinfrastructure (Hour of CI), a project creating a suite of self-paced, hour-long lessons aimed at helping learners in the areas of spatial, social, and environmental sciences take their first steps in the path toward cyberinfrastructure. Using collaboratively developed lessons written in Jupyter Notebooks, the Hour of CI aims to lower barriers to cyberinfrastructure for next-generation scientists and scholars from broad and diverse backgrounds. Early findings based on a pilot of four lessons suggest our approach has created engaging and appropriately challenging lessons for diverse learners. The project will continue developing lessons to help learners build cyber literacy for GIScience and prepare them to tackle global problems.
{"title":"The Hour of Cyberinfrastructure (Hour of CI): Early Findings from Pilot Study to Build Cyber Literacy for GIScience","authors":"Eric Shook, F. Bowlick, Anand Padmanabhan, Karen K. Kemp","doi":"10.1109/eduhpc54835.2021.00007","DOIUrl":"https://doi.org/10.1109/eduhpc54835.2021.00007","url":null,"abstract":"This paper provides an overview of the Hour of Cyberinfrastructure (Hour of CI), a project creating a suite of self-paced, hour-long lessons aimed at helping learners in the areas of spatial, social, and environmental sciences take their first steps in the path toward cyberinfrastructure. Using collaboratively developed lessons written in Jupyter Notebooks, the Hour of CI aims to lower barriers to cyberinfrastructure for next-generation scientists and scholars from broad and diverse backgrounds. Early findings based on a pilot of four lessons suggest our approach has created engaging and appropriately challenging lessons for diverse learners. The project will continue developing lessons to help learners build cyber literacy for GIScience and prepare them to tackle global problems.","PeriodicalId":318900,"journal":{"name":"2021 IEEE/ACM Ninth Workshop on Education for High Performance Computing (EduHPC)","volume":"389 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114907002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
There is a growing realization that optimization can be applied to many aspects of the software development process a research area known as Search Based Software Engineering (SBSE). Search Based Software Testing — one of the largest research areas within SBSE — is the process of using search-based optimization algorithms to specifically address problems in software testing. SBST has been applied to a wide variety of testing goals including structural, functional, non-functional and statebased properties. Many approaches to testing and a wide diverse range of development domains have been addressed, including exceptions, interactions, integration, mutation, regression, and web applications.
{"title":"Message from the Workshop Chairs","authors":"N. Feamster, J. Rexford, W. Willinger","doi":"10.1109/hpcc.2009.108","DOIUrl":"https://doi.org/10.1109/hpcc.2009.108","url":null,"abstract":"There is a growing realization that optimization can be applied to many aspects of the software development process a research area known as Search Based Software Engineering (SBSE). Search Based Software Testing — one of the largest research areas within SBSE — is the process of using search-based optimization algorithms to specifically address problems in software testing. SBST has been applied to a wide variety of testing goals including structural, functional, non-functional and statebased properties. Many approaches to testing and a wide diverse range of development domains have been addressed, including exceptions, interactions, integration, mutation, regression, and web applications.","PeriodicalId":318900,"journal":{"name":"2021 IEEE/ACM Ninth Workshop on Education for High Performance Computing (EduHPC)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122614007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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