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International Journal of Reconfigurable Computing最新文献

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Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates 动态可重构计算:大规模缺陷率下同质多核的替代方案
IF 4.3 Q1 Computer Science Pub Date : 2011-03-02 DOI: 10.1155/2011/452589
M. Pereira, L. Carro
The aggressive scaling of CMOS technology has increased the density and allowed the integration of multiple processors into a single chip. Although solutions based on MPSoC architectures can increase application's speed through TLP exploitation, this speedup is still limited to the amount of parallelism available in the application, as demonstrated by Amdahl's Law. Moreover, with the continuous shrinking of device features, very aggressive defect rates are expected for new technologies. Under high defect rates a large amount of processors of the MPSoC will be susceptible to defects and consequently will fail, not only reducing yield but also severely affecting the expected performance. This paper presents a run-time adaptive architecture that allows software execution even under aggressive defect rates. The proposed architecture can accelerate not only highly parallel applications but also sequential ones, and it is a heterogeneous solution to overcome the performance penalty that is imposed to homogeneous MPSoCs under massive defect rates.
CMOS技术的积极扩展增加了密度,并允许将多个处理器集成到单个芯片中。尽管基于MPSoC架构的解决方案可以通过利用TLP来提高应用程序的速度,但正如Amdahl定律所证明的那样,这种加速仍然受到应用程序中可用并行性的限制。此外,随着设备功能的不断缩小,新技术的缺陷率预计会非常高。在高缺陷率的情况下,MPSoC的大量处理器将容易出现缺陷,从而导致失效,不仅降低了成品率,而且严重影响了预期性能。本文提出了一种运行时自适应架构,即使在高缺陷率下也允许软件执行。所提出的体系结构不仅可以加速高度并行的应用程序,还可以加速顺序应用程序,并且它是一种异构解决方案,可以克服在高缺品率下同构mpsoc所带来的性能损失。
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引用次数: 4
Exploration of Heterogeneous FPGA Architectures 异构FPGA架构的探索
IF 4.3 Q1 Computer Science Pub Date : 2010-01-01 DOI: 10.1155/2011/121404
Umer Farooq, H. Parvez, H. Mehrez, Z. Marrakchi
Mesh-based heterogeneous FPGAs are commonly used in industry and academia due to their area, speed, and power benefits over their homogeneous counterparts. These FPGAs contain a mixture of logic blocks and hard blocks where hard blocks are arranged in fixed columns as they offer an easy and compact layout. However, the placement of hard-blocks in fixed columns can potentially lead to underutilization of logic and routing resources and this problem is further aggravated with increase in the types of hardblocks. This work explores and compares different floor-planning techniques of mesh-based FPGA to determine their effect on the area, performance, and power of the architecture. A tree-based architecture is also presented; unlike mesh-based architecture, the floor-planning of heterogeneous tree-based architecture does not affect its routing requirements due to its hierarchical structure. Both mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.
基于网格的异构fpga由于其面积、速度和功率优于同类fpga,在工业和学术界中广泛使用。这些fpga包含逻辑块和硬块的混合物,其中硬块排列在固定列中,因为它们提供了一个简单而紧凑的布局。但是,将硬块放置在固定列中可能会导致逻辑和路由资源的利用不足,并且随着硬块类型的增加,这个问题会进一步恶化。这项工作探索并比较了基于网格的FPGA的不同地板规划技术,以确定它们对架构的面积、性能和功耗的影响。提出了一种基于树的体系结构;与基于网格的体系结构不同,异构树的分层规划不影响其路由需求。在三组基准电路中对网格和树结构进行了评估。实验结果表明,基于网格的FPGA地板规划比基于列的地板规划更灵活,可以获得更好的效果。结果表明,与网格FPGA的不同布局相比,树型结构具有更好的面积、性能和功耗。
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引用次数: 26
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International Journal of Reconfigurable Computing
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