An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell’s quiescent current to a multiple of a reference current and each cell’s static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA.
本文介绍了一种基于数字标准单元设计模拟构件的方法。通过确保标准单元库中的每个 CMOS 逆变器都以定义明确的静态电流和输出电压工作，所建议的方法使构建可抵御 PVT 变化的模拟电路成为可能。该方法使用连接到标准单元逆变器 p 沟道和 n 沟道 MOS 晶体管源极的本地电源电压作为控制输入。它以自适应电源电压发生器 (ASVG) 可重复使用模块为基础，这些模块与数字应用中用于处理工艺变化的模块相当。所有用于模拟功能的标准单元逆变器都能接收由 ASVG 产生的本地电源电压，从而将每个单元的静态电流设置为参考电流的倍数，并将每个单元的静态输出电压设置为适当的参考电压。本文介绍了 ASVG 模块的完整定制设计和 ASVG 反馈回路的理论研究。此外，还通过设计一个完全可合成的两级运算跨导放大器 (OTA) 提供了一个应用实例。OTA 和 ASV 发生器均采用了 TSMC 180 nm CMOS 技术。仿真结果表明，所提出的方法可以准确设置标准单元逆变器的静态电流，从而显著降低 PVT 变化对基于标准单元的两级 OTA 的主要性能参数的影响。
{"title":"An Ultra-Low-Voltage Approach to Accurately Set the Quiescent Current of Digital Standard Cells Used for Analog Design and Its Application on an Inverter-Based Operational Transconductance Amplifier","authors":"Riccardo Della Sala, F. Centurelli, G. Scotti","doi":"10.3390/jlpea14030039","DOIUrl":"https://doi.org/10.3390/jlpea14030039","url":null,"abstract":"An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell’s quiescent current to a multiple of a reference current and each cell’s static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA.","PeriodicalId":506045,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":"36 3","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141810080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Widartha, Ilkyeun Ra, Su-Yeon Lee, Chang-Soo Kim
Smart lighting control systems represent an advanced approach to reducing energy use. These systems leverage advanced technology to provide users with better control over their lighting, allowing them to manually, remotely, and automatically modify the brightness, color, and timing of their lights. In this study, we aimed to enhance the energy efficiency of smart lighting systems by using light source data. A multifaceted approach was employed, involving the following three scenarios: sensing device, daylight data, and a combination of both. A low-cost sensor and third-party API were used for data collection, and a prototype application was developed for real-time monitoring. The results showed that combining sensor and daylight data effectively reduced energy consumption, and the rule-based algorithm further optimized energy usage. The prototype application provided real-time monitoring and actionable insights, thus contributing to overall energy optimization.
{"title":"Advancing Smart Lighting: A Developmental Approach to Energy Efficiency through Brightness Adjustment Strategies","authors":"V. Widartha, Ilkyeun Ra, Su-Yeon Lee, Chang-Soo Kim","doi":"10.3390/jlpea14010006","DOIUrl":"https://doi.org/10.3390/jlpea14010006","url":null,"abstract":"Smart lighting control systems represent an advanced approach to reducing energy use. These systems leverage advanced technology to provide users with better control over their lighting, allowing them to manually, remotely, and automatically modify the brightness, color, and timing of their lights. In this study, we aimed to enhance the energy efficiency of smart lighting systems by using light source data. A multifaceted approach was employed, involving the following three scenarios: sensing device, daylight data, and a combination of both. A low-cost sensor and third-party API were used for data collection, and a prototype application was developed for real-time monitoring. The results showed that combining sensor and daylight data effectively reduced energy consumption, and the rule-based algorithm further optimized energy usage. The prototype application provided real-time monitoring and actionable insights, thus contributing to overall energy optimization.","PeriodicalId":506045,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":"24 17","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139528823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher power due to larger memory bitcells. Gain-cell eDRAM is a high-density alternative for multi-ported operation with a small silicon footprint. However, conventional gain-cell memories have limited data availability, as they require periodic refresh operations to maintain their data. In this paper, we propose a novel multi-ported gain-cell design, which provides up-to N read ports and M independent write ports (NRMW). In addition, the proposed design features a configurable mode of operation, supporting a hidden refresh mechanism for improved memory availability, as well as a novel opportunistic refresh port approach. An 8kbit memory macro was implemented using a four-transistor bitcell with four ports (2R2W) in a 28 nm FD-SOI technology, offering up-to a 3× reduction in bitcell area compared to other dual-ported SRAM memory options, while also providing 100% memory availability, as opposed to conventional dynamic memories, which are hindered by limited availability.
{"title":"Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism","authors":"R. Golman, R. Giterman, A. Teman","doi":"10.3390/jlpea14010002","DOIUrl":"https://doi.org/10.3390/jlpea14010002","url":null,"abstract":"Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher power due to larger memory bitcells. Gain-cell eDRAM is a high-density alternative for multi-ported operation with a small silicon footprint. However, conventional gain-cell memories have limited data availability, as they require periodic refresh operations to maintain their data. In this paper, we propose a novel multi-ported gain-cell design, which provides up-to N read ports and M independent write ports (NRMW). In addition, the proposed design features a configurable mode of operation, supporting a hidden refresh mechanism for improved memory availability, as well as a novel opportunistic refresh port approach. An 8kbit memory macro was implemented using a four-transistor bitcell with four ports (2R2W) in a 28 nm FD-SOI technology, offering up-to a 3× reduction in bitcell area compared to other dual-ported SRAM memory options, while also providing 100% memory availability, as opposed to conventional dynamic memories, which are hindered by limited availability.","PeriodicalId":506045,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":"63 2","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139386887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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