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A Convolutional Neural Network Pipeline For Multi-Temporal Retinal Image Registration. 基于卷积神经网络管道的多时间视网膜图像配准。
Pub Date : 2021-10-01 Epub Date: 2021-11-25 DOI: 10.1109/isocc53507.2021.9613906
Chi-Jui Ho, Yiqian Wang, Junkang Zhang, Truong Nguyen, Cheolhong An

A sequence of images is usually captured to observe the change of health status in medical diagnosis. However, an image sequence taken over year usually suffers from severe deformation, making it time-consuming for physicians to match corresponding patterns. In this paper, we propose a coarse-to-fine pipeline for retinal image registration based on convolutional neural network. By leveraging the three components of the pipeline: feature matching, outlier rejection, and local registration, we recover the deformation and accurately align multi-temporal image sequences. Experimental results show that the proposed network is robust to severe deformation as well as illumination and contrast variations. With the proposed registration pipeline, the change of image patterns over time can be identified through visual analysis.

在医学诊断中,通常通过采集一系列图像来观察健康状况的变化。然而,一年以上拍摄的图像序列通常会有严重的变形,这使得医生匹配相应的模式非常耗时。本文提出了一种基于卷积神经网络的粗到精的视网膜图像配准方法。通过利用管道的三个组成部分:特征匹配、离群值抑制和局部配准,我们恢复了变形并精确对齐了多时相图像序列。实验结果表明,该网络对严重变形、光照和对比度变化具有较强的鲁棒性。利用所提出的配准流水线,可以通过视觉分析识别图像模式随时间的变化。
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引用次数: 0
Comparative analysis of FinFET and Planar MOSFET SRAMs FinFET与平面MOSFET sram之比较分析
Pub Date : 2020-01-01 DOI: 10.1109/ISOCC50952.2020.9333122
K. Pradeep, B. Mohith, P. ManjunathK., S. SunitaM.
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引用次数: 0
A 0.5-V sub-mW energy-efficient receiver in 0.18-μm CMOS for IoT applications 用于物联网应用的0.5 v亚毫瓦节能接收器,采用0.18 μm CMOS
Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799835
Tse-Wei Wang, Yi-Lin Tsai, Chong-Rong Lee, Fu-Lian Hung, Tsung-Hsien Lin
A 0.5-V differential BPSK (D-BPSK) receiver (RX) realized in 0.18-μm CMOS is presented in this paper. This RX adopts the injection-locking technique to demodulate the received signal. The core of this RX is an injection-locked oscillator which converts the input phase transition to envelope variation for demodulation. This work is fabricated in TSMC 0.18-μm CMOS technology. The proposed RX consumes 0.97 mW from a 0.5-V supply. The sensitivity is −45 dBm. At 10-Mbps data rate, the energy efficiency is 97 pJ/b.
提出了一种采用0.18 μm CMOS芯片实现的0.5 v差分BPSK (D-BPSK)接收机。该RX采用注入锁定技术对接收信号进行解调。该RX的核心是一个注入锁定振荡器,它将输入相变转换为包络变化进行解调。该器件采用TSMC 0.18-μm CMOS工艺。提议的RX从0.5 v电源消耗0.97兆瓦。灵敏度为−45dbm。在10mbps的数据速率下,能量效率为97 pJ/b。
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引用次数: 0
A 166.7 Mhz 1920×1080 60fps H.264/SVC video decoder 166.7 Mhz 1920×1080 60fps H.264/SVC视频解码器
Pub Date : 2011-11-01 DOI: 10.1109/ISOCC.2011.6138764
Seunghyun Cho, Seongmo Park, N. Eum
In this paper, a hardware design of an H.264/SVC video decoder is presented. Large size inter-coded pictures in a high frame rate require a high external memory bandwidth in decoding process. Inter-layer predictions of SVC further increase data transfer from or to an external memory. A cache-based motion compensation to sufficiently reduce overhead cycles for external SDRAM access and the bandwidth requirement is proposed. Much variation of macroblock processing cycles for CABAC decoding is another obstacle to design a SVC video decoder with macroblock based pipelining scheme. A frame level delaying method is proposed to remove the cycle variations, so that the decoder works with a steady throughput. The proposed SVC decoder shows HD1080p 60fps of decoding capability operating at 166.7MHz.
本文介绍了一种H.264/SVC视频解码器的硬件设计。大尺寸高帧率的互编码图像在解码过程中需要较高的外部存储带宽。SVC的层间预测进一步增加了从外部存储器到外部存储器的数据传输。提出了一种基于缓存的运动补偿,以充分减少外部SDRAM访问的开销周期和带宽需求。CABAC解码的宏块处理周期变化较大是设计基于宏块的SVC视频解码器的另一个障碍。提出了一种帧级延迟方法来消除周期变化,使解码器具有稳定的吞吐量。提出的SVC解码器显示HD1080p 60fps的解码能力,工作在166.7MHz。
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引用次数: 0
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International SoC Design Conference. International SoC Design Conference
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