Pub Date : 2010-06-15DOI: 10.1109/AHS.2010.5546241
M. Samie, G. Dragffy, A. Pipe
This paper presents a novel bio-inspired self-test technique for the implementation of evolvable fault tolerant systems based on the structure, behavior and processes observed in prokaryote unicellular organisms. Such Unitronic (unicellular electronic) artificial systems are implemented by FPGA-like bio-inspired cellular arrays and made up of structurally identical cells. All cells possess self-diagnostic and self-healing capability. Our underlying conceptual postulation is: if it can be guaranteed that during the test phase a cell, the internal functionality of which is configured with a complementary input sequence, demonstrates the same functionality, as that with the original sequence during its normal mode of operation, then the cell is fault free, otherwise it is faulty. Our proposed self-test can evaluate all stuck-at-zero and stuck-at-one faults of the system if at any time only one fault exists. Hardware redundancy is optimised because the same hardware, by simple reconfiguration is able to test itself and thus eliminates the need of duplicated, triplicated hardware.
{"title":"Bio-inspired self-test for evolvable fault tolerant hardware systems","authors":"M. Samie, G. Dragffy, A. Pipe","doi":"10.1109/AHS.2010.5546241","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546241","url":null,"abstract":"This paper presents a novel bio-inspired self-test technique for the implementation of evolvable fault tolerant systems based on the structure, behavior and processes observed in prokaryote unicellular organisms. Such Unitronic (unicellular electronic) artificial systems are implemented by FPGA-like bio-inspired cellular arrays and made up of structurally identical cells. All cells possess self-diagnostic and self-healing capability. Our underlying conceptual postulation is: if it can be guaranteed that during the test phase a cell, the internal functionality of which is configured with a complementary input sequence, demonstrates the same functionality, as that with the original sequence during its normal mode of operation, then the cell is fault free, otherwise it is faulty. Our proposed self-test can evaluate all stuck-at-zero and stuck-at-one faults of the system if at any time only one fault exists. Hardware redundancy is optimised because the same hardware, by simple reconfiguration is able to test itself and thus eliminates the need of duplicated, triplicated hardware.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132645120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-15DOI: 10.1109/AHS.2010.5546233
M. Pelcat, J. Nezan, Slaheddine Aridhi
The Long Term Evolution (LTE) is the next generation cellular system of 3GPP, where every subframe (1 millisecond duration), a base station receives information from up to one hundred users. Multicore heterogeneous embedded systems with Digital Signal Processors (DSP) and coprocessors are power efficient solutions which decode the LTE uplink signals and encode the downlink LTE signals in base stations. The LTE Physical Uplink Shared Channel (PUSCH) uses a dynamic algorithm, as its multicore scheduling must be adapted every subframe to the number of transmitting users and to the data rate of the services they require. To solve this particular issue of the dynamic deployment while maintaining low latency, one approach is to find efficient on-the-fly solutions using techniques such as graph generation and scheduling. This approach is opposed to a fully static scheduling of predefined cases, approach currently used in the UMTS deployments. We show that the fully static approach is not suitable for the LTE PUSCH and that present DSP cores are powerful enough to recompute an efficient adaptive schedule for the application most complex cases in real-time.
{"title":"Adaptive multicore scheduling for the LTE uplink","authors":"M. Pelcat, J. Nezan, Slaheddine Aridhi","doi":"10.1109/AHS.2010.5546233","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546233","url":null,"abstract":"The Long Term Evolution (LTE) is the next generation cellular system of 3GPP, where every subframe (1 millisecond duration), a base station receives information from up to one hundred users. Multicore heterogeneous embedded systems with Digital Signal Processors (DSP) and coprocessors are power efficient solutions which decode the LTE uplink signals and encode the downlink LTE signals in base stations. The LTE Physical Uplink Shared Channel (PUSCH) uses a dynamic algorithm, as its multicore scheduling must be adapted every subframe to the number of transmitting users and to the data rate of the services they require. To solve this particular issue of the dynamic deployment while maintaining low latency, one approach is to find efficient on-the-fly solutions using techniques such as graph generation and scheduling. This approach is opposed to a fully static scheduling of predefined cases, approach currently used in the UMTS deployments. We show that the fully static approach is not suitable for the LTE PUSCH and that present DSP cores are powerful enough to recompute an efficient adaptive schedule for the application most complex cases in real-time.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127777087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-15DOI: 10.1109/AHS.2010.5546271
Matthias Brugger, Ferdinand Kemeth
We introduce different techniques, to adapt the update rate of a Real Time Locating System (RTLS) using Angle of Arrival (AoA) and Round Trip Time (RTT). A dedicated algorithm is implemented to detect the speed of walking of a person by exploiting data on the steps from a 3-dimensional accelerometer. Its implementation is described and the results of two experiments are discussed demonstrating the gain of the adaptation in terms of an increased channel capacity.
{"title":"Locating rate adaptation by evaluating movement specific parameters","authors":"Matthias Brugger, Ferdinand Kemeth","doi":"10.1109/AHS.2010.5546271","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546271","url":null,"abstract":"We introduce different techniques, to adapt the update rate of a Real Time Locating System (RTLS) using Angle of Arrival (AoA) and Round Trip Time (RTT). A dedicated algorithm is implemented to detect the speed of walking of a person by exploiting data on the steps from a 3-dimensional accelerometer. Its implementation is described and the results of two experiments are discussed demonstrating the gain of the adaptation in terms of an increased channel capacity.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133534665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-15DOI: 10.1109/AHS.2010.5546259
J. Barrera, G. Huff
This paper examines the frequency reconfiguration of an SIW bandpass filter for frequency-agile operations. Dispersions of dielectric nanoparticles are used as vertically aligned fluidic material perturbations in these devices to provide electromagnetic agility for reconfiguration. Analytical modeling, simulated, and measured data for a single-pole X-band bandpass SIW filter.
{"title":"An adaptive SIW filter using vertically-orientated fluidic material perturbations","authors":"J. Barrera, G. Huff","doi":"10.1109/AHS.2010.5546259","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546259","url":null,"abstract":"This paper examines the frequency reconfiguration of an SIW bandpass filter for frequency-agile operations. Dispersions of dielectric nanoparticles are used as vertically aligned fluidic material perturbations in these devices to provide electromagnetic agility for reconfiguration. Analytical modeling, simulated, and measured data for a single-pole X-band bandpass SIW filter.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134504930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-15DOI: 10.1109/AHS.2010.5546231
S. Narasimhan, Somnath Paul, R. Chakraborty, F. Wolff, C. Papachristou, D. Weyer, S. Bhunia
Post-silicon process compensation or “healing” of integrated circuits (ICs) has emerged as an effective approach to improve yield and reliability under parameter variations. In a System-on-Chip (SoC) comprising of multiple cores, different cores can experience different process shift due to local within-die variations. Furthermore, the cores are likely to have different sensitivities with respect to system power dissipation and system output parameters such as quality of service or throughput. Post-silicon healing has been addressed earlier at core level using various compensation approaches. In this paper, we present a system level healing algorithm for compensating SoC chips for a specific output parameter under power constraint. We formulate the healing problem as an ordinal optimization problem, where individual cores need to be assigned the right amount of healing that satisfies the target system performance and power requirement. Next, we propose an efficient solution to the problem using a priori design-time information about the relative sensitivities of the cores to system performance and power. Simulation results for example systems show that the proposed healing approach can achieve higher parametric yield and better settling time compared to conventional healing approaches.
{"title":"System level self-healing for parametric yield and reliability improvement under power bound","authors":"S. Narasimhan, Somnath Paul, R. Chakraborty, F. Wolff, C. Papachristou, D. Weyer, S. Bhunia","doi":"10.1109/AHS.2010.5546231","DOIUrl":"https://doi.org/10.1109/AHS.2010.5546231","url":null,"abstract":"Post-silicon process compensation or “healing” of integrated circuits (ICs) has emerged as an effective approach to improve yield and reliability under parameter variations. In a System-on-Chip (SoC) comprising of multiple cores, different cores can experience different process shift due to local within-die variations. Furthermore, the cores are likely to have different sensitivities with respect to system power dissipation and system output parameters such as quality of service or throughput. Post-silicon healing has been addressed earlier at core level using various compensation approaches. In this paper, we present a system level healing algorithm for compensating SoC chips for a specific output parameter under power constraint. We formulate the healing problem as an ordinal optimization problem, where individual cores need to be assigned the right amount of healing that satisfies the target system performance and power requirement. Next, we propose an efficient solution to the problem using a priori design-time information about the relative sensitivities of the cores to system performance and power. Simulation results for example systems show that the proposed healing approach can achieve higher parametric yield and better settling time compared to conventional healing approaches.","PeriodicalId":101655,"journal":{"name":"2010 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125078971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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