Uniform Random Number Generator (URNG) is a key element in most applications which run on FPGA based hardware accelerators. As multi-bits is required and a normal LFSR could only generate one bit per cycle, more than one LFSR is needed in a URNG. In this paper, we introduce a new kind of URNG using Leap-Ahead LFSR Architecture which could generate an m-bits random number per cycle using only one LFSR. We analyze its architecture, present the expression of the period and point out how to choose the taps of the LFSR. Finally, a 18-bits URNG is implemented on Xilinx Vertex ¿ FPGA.. By comparison, the Leap-Ahead LFSR Architecture URNG consumes less than 40 slices which is only 10% of what the Multi-LFSRs architecture consumes and acquires very good Area Time performance and Throughput performance that are 2.18×10-9 slices×sec per bit and 17.87×109 bits per sec.
均匀随机数发生器(Uniform Random Number Generator, URNG)是大多数基于FPGA的硬件加速器应用的关键部件。由于需要多比特，而一个正常的LFSR每个周期只能产生一个比特，因此在一个URNG中需要多个LFSR。本文介绍了一种使用跃进LFSR架构的新型URNG，它可以仅使用一个LFSR每个周期生成一个m位随机数。分析了LFSR的结构，提出了LFSR的时代表现，并指出了如何选择LFSR的开关。最后，在Xilinx Vertex¿FPGA上实现了一个18位URNG。相比之下，Leap-Ahead LFSR架构URNG消耗不到40片，仅为multi -LFSR架构消耗的10%，并且获得了非常好的区域时间性能和吞吐量性能，分别为2.18×10-9 slices×sec / bit和17.87×109 bits / s。
{"title":"Uniform Random Number Generator Using Leap Ahead LFSR Architecture","authors":"Gu Xiao-chen, Zhang Min-xuan","doi":"10.1109/ICCCS.2009.11","DOIUrl":"https://doi.org/10.1109/ICCCS.2009.11","url":null,"abstract":"Uniform Random Number Generator (URNG) is a key element in most applications which run on FPGA based hardware accelerators. As multi-bits is required and a normal LFSR could only generate one bit per cycle, more than one LFSR is needed in a URNG. In this paper, we introduce a new kind of URNG using Leap-Ahead LFSR Architecture which could generate an m-bits random number per cycle using only one LFSR. We analyze its architecture, present the expression of the period and point out how to choose the taps of the LFSR. Finally, a 18-bits URNG is implemented on Xilinx Vertex ¿ FPGA.. By comparison, the Leap-Ahead LFSR Architecture URNG consumes less than 40 slices which is only 10% of what the Multi-LFSRs architecture consumes and acquires very good Area Time performance and Throughput performance that are 2.18×10-9 slices×sec per bit and 17.87×109 bits per sec.","PeriodicalId":103274,"journal":{"name":"2009 International Conference on Computer and Communications Security","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129095023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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