Pub Date : 2001-09-12DOI: 10.1109/ASIC.2001.954681
C.R. Sotiriou
Conventional asynchronous control circuit design is complex because potential designs must be analysed for the existence of hazards and state variable races, as these may cause incorrect circuit operation. We present the innovative CMOS direct-mapped asynchronous circuit design approach, which, by defining a one-to-one mapping between state diagram and CMOS circuit implementation, removes the need for race and hazard circuit analysis It allows for regular, fast, multiple-input-change, nonfundamental mode asynchronous control circuits to be realised in CMOS technology.
{"title":"Direct-mapped asynchronous finite-state machines in CMOS technology","authors":"C.R. Sotiriou","doi":"10.1109/ASIC.2001.954681","DOIUrl":"https://doi.org/10.1109/ASIC.2001.954681","url":null,"abstract":"Conventional asynchronous control circuit design is complex because potential designs must be analysed for the existence of hazards and state variable races, as these may cause incorrect circuit operation. We present the innovative CMOS direct-mapped asynchronous circuit design approach, which, by defining a one-to-one mapping between state diagram and CMOS circuit implementation, removes the need for race and hazard circuit analysis It allows for regular, fast, multiple-input-change, nonfundamental mode asynchronous control circuits to be realised in CMOS technology.","PeriodicalId":103931,"journal":{"name":"Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125176465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-12DOI: 10.1109/ASIC.2001.954693
C. Traver, R. Reese, M. Thornton
A self-timed programmable architecture used for the implementation of Phased Logic (PL) systems is described. PL systems are automatically translated from clocked designs and result in self-timed circuits that are insensitive to delays between gates. The target implementation is a self-timed FPGA architecture composed of PL gates. A PL gate design based on a 4-input lookup table is presented. Power and performance estimates of two designs are given and are compared to their clocked counterparts.
{"title":"Cell designs for self-timed FPGAs","authors":"C. Traver, R. Reese, M. Thornton","doi":"10.1109/ASIC.2001.954693","DOIUrl":"https://doi.org/10.1109/ASIC.2001.954693","url":null,"abstract":"A self-timed programmable architecture used for the implementation of Phased Logic (PL) systems is described. PL systems are automatically translated from clocked designs and result in self-timed circuits that are insensitive to delays between gates. The target implementation is a self-timed FPGA architecture composed of PL gates. A PL gate design based on a 4-input lookup table is presented. Power and performance estimates of two designs are given and are compared to their clocked counterparts.","PeriodicalId":103931,"journal":{"name":"Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129800464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-12DOI: 10.1109/ASIC.2001.954717
G. Bertoni, L. Breveglieri, P. Fragneto
Multiplication in finite fields (Galois fields) is a basic operation for cryptography applications. Recent proposals for elliptic code cryptography, require efficient computation of multiplication in finite fields of type GF(2/sup n/) for large values of n (150, 200 bits). Digit-serial multiplier VLSI architectures are an attractive solution, being a compromise between purely parallel and serial ones. A comparative study of digit-serial multiplier VLSI architectures, for fields of type GF(2/sup n/), is carried out. Such architectures are reviewed, some further optimisations are proposed, and are then implemented in VHDL (CMOS cell library, 0.35 /spl mu/m, by ST Microelectronics). Figures of merit like time latency, silicon area and power consumption are evaluated by simulation with Synopsis tools, varying parameters like the size n of the field elements and the size k of the blocks of bits being processed in parallel by the digit-serial architectures.
{"title":"Comparative cost/performance evaluation of digit-serial multipliers for finite fields of type GF(2/sup n/)","authors":"G. Bertoni, L. Breveglieri, P. Fragneto","doi":"10.1109/ASIC.2001.954717","DOIUrl":"https://doi.org/10.1109/ASIC.2001.954717","url":null,"abstract":"Multiplication in finite fields (Galois fields) is a basic operation for cryptography applications. Recent proposals for elliptic code cryptography, require efficient computation of multiplication in finite fields of type GF(2/sup n/) for large values of n (150, 200 bits). Digit-serial multiplier VLSI architectures are an attractive solution, being a compromise between purely parallel and serial ones. A comparative study of digit-serial multiplier VLSI architectures, for fields of type GF(2/sup n/), is carried out. Such architectures are reviewed, some further optimisations are proposed, and are then implemented in VHDL (CMOS cell library, 0.35 /spl mu/m, by ST Microelectronics). Figures of merit like time latency, silicon area and power consumption are evaluated by simulation with Synopsis tools, varying parameters like the size n of the field elements and the size k of the blocks of bits being processed in parallel by the digit-serial architectures.","PeriodicalId":103931,"journal":{"name":"Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130633096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-12DOI: 10.1109/ASIC.2001.954697
G. Thirugnanam, N. Vijaykrishnan, M. J. Irwin
The Content Addressable Memory (CAM) is a class of memory that allows access by data instead of physical address. In this paper a novel low power CAM cell called the toggling match line CAM is introduced. It is shown to provide over 40% reduction in power consumed on read misses as compared to the basic CAM design.
{"title":"A novel low power CAM design","authors":"G. Thirugnanam, N. Vijaykrishnan, M. J. Irwin","doi":"10.1109/ASIC.2001.954697","DOIUrl":"https://doi.org/10.1109/ASIC.2001.954697","url":null,"abstract":"The Content Addressable Memory (CAM) is a class of memory that allows access by data instead of physical address. In this paper a novel low power CAM cell called the toggling match line CAM is introduced. It is shown to provide over 40% reduction in power consumed on read misses as compared to the basic CAM design.","PeriodicalId":103931,"journal":{"name":"Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)","volume":"43 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133023164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-12DOI: 10.1109/ASIC.2001.954731
T. Ruud, J. Wright
Pad design, the design of inputs and outputs of the integrated circuit that interface with the outside world, has increased in complexity multi-fold due to the increased variety of interfaces available today. This paper describes the creation of an I/O structure that is highly flexible in order to meet the needs of multivoltage and multi-swing circuits and which maintains common layouts suitable for gate array, standard cell and mixed signal designs.
{"title":"I/O design considerations for multi-application circuits","authors":"T. Ruud, J. Wright","doi":"10.1109/ASIC.2001.954731","DOIUrl":"https://doi.org/10.1109/ASIC.2001.954731","url":null,"abstract":"Pad design, the design of inputs and outputs of the integrated circuit that interface with the outside world, has increased in complexity multi-fold due to the increased variety of interfaces available today. This paper describes the creation of an I/O structure that is highly flexible in order to meet the needs of multivoltage and multi-swing circuits and which maintains common layouts suitable for gate array, standard cell and mixed signal designs.","PeriodicalId":103931,"journal":{"name":"Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133411719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-12DOI: 10.1109/ASIC.2001.954734
S. Shigematsu, H. Morimura, K. Machida
A new fingerprint sensing and digital-conversion scheme is proposed. In this scheme, transforming the sensed signal to a time axis widens the dynamic range of the signal, and the transformed signal is converted to the digital signal with variable range and offset. These features make it possible to sense various fingerprints clearly. We also propose a flow that adjusts the quality of the fingerprint image adaptively. The effectiveness of the scheme on sensing fingerprints clearly was confirmed by a test chip fabricated using 0.5-/spl mu/m CMOS/sensor process. This scheme assists in precise user identification for a safe and comfortable networked world.
提出了一种新的指纹传感和数字转换方案。在该方案中，将被测信号变换为时间轴，拓宽了信号的动态范围，并将变换后的信号转换为可变范围和偏移量的数字信号。这些特点使得清晰地感知各种指纹成为可能。我们还提出了一种自适应调整指纹图像质量的流程。采用0.5-/spl μ m CMOS/传感器工艺制作的测试芯片，验证了该方案在指纹传感上的有效性。该方案有助于精确的用户识别，为安全舒适的网络世界提供帮助。
{"title":"A new sensing and digital-conversion scheme with adaptive image-quality adjustment for a fingerprint sensor chip","authors":"S. Shigematsu, H. Morimura, K. Machida","doi":"10.1109/ASIC.2001.954734","DOIUrl":"https://doi.org/10.1109/ASIC.2001.954734","url":null,"abstract":"A new fingerprint sensing and digital-conversion scheme is proposed. In this scheme, transforming the sensed signal to a time axis widens the dynamic range of the signal, and the transformed signal is converted to the digital signal with variable range and offset. These features make it possible to sense various fingerprints clearly. We also propose a flow that adjusts the quality of the fingerprint image adaptively. The effectiveness of the scheme on sensing fingerprints clearly was confirmed by a test chip fabricated using 0.5-/spl mu/m CMOS/sensor process. This scheme assists in precise user identification for a safe and comfortable networked world.","PeriodicalId":103931,"journal":{"name":"Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128878421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-12DOI: 10.1109/ASIC.2001.954725
M. Martina, G. Masera, G. Piccinini, F. Vacca, M. Zamboni
In this paper a novel VLSI Reed Solomon decoder architecture is presented. During the design flow, particular care has been posed to the methodology used in order to grant a great degree of reusability. The obtained decoder core is very suitable for complex System On Chip (SoC) based applications, common in networking environments. In fact, thanks to the high reliability allowed by advanced channel coding techniques, the architecture developed has interesting figures of simplicity and speed. Logic synthesis on a FPGA device has shown an operating frequency up to 86 MHz with a core area of just 447 cells.
{"title":"VLSI Reed Solomon decoder architecture for networked multimedia applications","authors":"M. Martina, G. Masera, G. Piccinini, F. Vacca, M. Zamboni","doi":"10.1109/ASIC.2001.954725","DOIUrl":"https://doi.org/10.1109/ASIC.2001.954725","url":null,"abstract":"In this paper a novel VLSI Reed Solomon decoder architecture is presented. During the design flow, particular care has been posed to the methodology used in order to grant a great degree of reusability. The obtained decoder core is very suitable for complex System On Chip (SoC) based applications, common in networking environments. In fact, thanks to the high reliability allowed by advanced channel coding techniques, the architecture developed has interesting figures of simplicity and speed. Logic synthesis on a FPGA device has shown an operating frequency up to 86 MHz with a core area of just 447 cells.","PeriodicalId":103931,"journal":{"name":"Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114794192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-12DOI: 10.1109/ASIC.2001.954672
S. Han, T. Han, Yong-Chan Kim, Chul Kim, Kyung-Hal Lee, I. Paik, Kyung-Ho Kim, Yong-Seok Kim, Sang-Woon Jung
We present the CDMA2000-1x compliant mobile station modem chip implemented in a 0.18-/spl mu/m CMOS technology. An ARM940T cached processor, a TEAKLITE DSP core, and other peripheral IPs are integrated with the baseband modem. The related SoC design techniques and verification methodologies are also described. The functionality and performance of this chip have been tested by building a handset and applying IS-98C test procedures using the Agilent 8960 base station simulator.
我们提出了一种兼容CDMA2000-1x的移动基站调制解调器芯片，该芯片采用0.18-/spl μ m CMOS技术实现。该基带调制解调器集成了ARM940T缓存处理器、TEAKLITE DSP核心和其他外设ip。本文还介绍了相关的SoC设计技术和验证方法。该芯片的功能和性能已经通过构建手机和应用IS-98C测试程序使用安捷伦8960基站模拟器进行了测试。
{"title":"A mobile station modem VLSI for CDMA2000-1x","authors":"S. Han, T. Han, Yong-Chan Kim, Chul Kim, Kyung-Hal Lee, I. Paik, Kyung-Ho Kim, Yong-Seok Kim, Sang-Woon Jung","doi":"10.1109/ASIC.2001.954672","DOIUrl":"https://doi.org/10.1109/ASIC.2001.954672","url":null,"abstract":"We present the CDMA2000-1x compliant mobile station modem chip implemented in a 0.18-/spl mu/m CMOS technology. An ARM940T cached processor, a TEAKLITE DSP core, and other peripheral IPs are integrated with the baseband modem. The related SoC design techniques and verification methodologies are also described. The functionality and performance of this chip have been tested by building a handset and applying IS-98C test procedures using the Agilent 8960 base station simulator.","PeriodicalId":103931,"journal":{"name":"Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125866810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-12DOI: 10.1109/ASIC.2001.954690
J. Chi, Mely Chen Chi
The authors present a new router which can be used to route power and ground nets through the use of double metal layers. It was developed for integrated circuit designs. A chip may have multiple power/ground pads located on any side of the chip. Multiple trees may be constructed for power or ground nets to consume as small as possible routing resource. The routing algorithm used is a modification of Dijkstra's algorithm, which searches for the shortest path between a pin and a pad. It uses a new metric for the cost function. The cost is the total area of routing wires and the additional pitch region due to the routing path. Corner reduction is also considered. This new metric is more accurate in measuring the quality of routing than wire length/area alone because the reserved pitch region may not be used for routing any other net. The power and ground nets are routed under the constraints of electromigration and voltage drop of the chip. Experimental results are shown.
{"title":"A new two-layer power/ground router for VLSI layout","authors":"J. Chi, Mely Chen Chi","doi":"10.1109/ASIC.2001.954690","DOIUrl":"https://doi.org/10.1109/ASIC.2001.954690","url":null,"abstract":"The authors present a new router which can be used to route power and ground nets through the use of double metal layers. It was developed for integrated circuit designs. A chip may have multiple power/ground pads located on any side of the chip. Multiple trees may be constructed for power or ground nets to consume as small as possible routing resource. The routing algorithm used is a modification of Dijkstra's algorithm, which searches for the shortest path between a pin and a pad. It uses a new metric for the cost function. The cost is the total area of routing wires and the additional pitch region due to the routing path. Corner reduction is also considered. This new metric is more accurate in measuring the quality of routing than wire length/area alone because the reserved pitch region may not be used for routing any other net. The power and ground nets are routed under the constraints of electromigration and voltage drop of the chip. Experimental results are shown.","PeriodicalId":103931,"journal":{"name":"Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132156375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-09-12DOI: 10.1109/ASIC.2001.954666
M. Kanteti, A. Titus
A prototype sensor fusion system is presented that demonstrates the feasibility of utilizing analog VLSI smart pixels. The system is implemented on a chip and provides information as to the location and movement of a source that emits light and a 1 kHz acoustic signal. The components are simulated and the complete system is a 16 pixel light sensor. and three block acoustic sensor that uses three (triangulated) external microphones. The results show that low-level fusion is successful, and that high-level fusion is possible, given the design of the subsystems. The system is laid out using a MOSIS Tiny Chip padframe, which is fabrication-ready.
{"title":"Light and sound data fusion in analog VLSI","authors":"M. Kanteti, A. Titus","doi":"10.1109/ASIC.2001.954666","DOIUrl":"https://doi.org/10.1109/ASIC.2001.954666","url":null,"abstract":"A prototype sensor fusion system is presented that demonstrates the feasibility of utilizing analog VLSI smart pixels. The system is implemented on a chip and provides information as to the location and movement of a source that emits light and a 1 kHz acoustic signal. The components are simulated and the complete system is a 16 pixel light sensor. and three block acoustic sensor that uses three (triangulated) external microphones. The results show that low-level fusion is successful, and that high-level fusion is possible, given the design of the subsystems. The system is laid out using a MOSIS Tiny Chip padframe, which is fabrication-ready.","PeriodicalId":103931,"journal":{"name":"Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129185858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：