Pub Date : 2021-09-08DOI: 10.1109/FDL53530.2021.9568378
Jobish John, Amrita Ghosal, T. Margaria, D. Pesch
Automation systems involve a range of cyber-physical system components such as sensors, actuators, control equipment, machines, robots, AGVs, etc. Seamless interoperability among these entities is a significant challenge. A well-designed Industrial Internet of Things (IIoT) platform at the network edge can offer several services by acting as a transformation engine between these field devices and various enterprise applications. We consider the EdgeX Foundry platform as such an IIoT middleware, discuss how EdgeX can provide ready-to-use integration of IoT devices, and show how we connect it with a low-code XMDD coordination layer that interfaces with EdgeX microservices through a Native DSL mechanism. We consider this technology landscape from the point of view of a building automation system example that supports high reconfigurability and security. We show how to produce all the essential elements of a complex Web based application to control the considered building systems. We demonstrate various features of the application's data and process models, how DSLs play a role at various levels, and how to add security capabilities that go beyond the cross-layer concerns and mechanisms offered by EdgeX. To this end, we introduce a declarative policy layer to be implemented using the open source ADD-Lib in form of an additional DSL for Attribute Based Encryption, with the aim of further enriching the capabilities around the EdgeX platform.
{"title":"DSLs for Model Driven Development of Secure Interoperable Automation Systems with EdgeX Foundry","authors":"Jobish John, Amrita Ghosal, T. Margaria, D. Pesch","doi":"10.1109/FDL53530.2021.9568378","DOIUrl":"https://doi.org/10.1109/FDL53530.2021.9568378","url":null,"abstract":"Automation systems involve a range of cyber-physical system components such as sensors, actuators, control equipment, machines, robots, AGVs, etc. Seamless interoperability among these entities is a significant challenge. A well-designed Industrial Internet of Things (IIoT) platform at the network edge can offer several services by acting as a transformation engine between these field devices and various enterprise applications. We consider the EdgeX Foundry platform as such an IIoT middleware, discuss how EdgeX can provide ready-to-use integration of IoT devices, and show how we connect it with a low-code XMDD coordination layer that interfaces with EdgeX microservices through a Native DSL mechanism. We consider this technology landscape from the point of view of a building automation system example that supports high reconfigurability and security. We show how to produce all the essential elements of a complex Web based application to control the considered building systems. We demonstrate various features of the application's data and process models, how DSLs play a role at various levels, and how to add security capabilities that go beyond the cross-layer concerns and mechanisms offered by EdgeX. To this end, we introduce a declarative policy layer to be implemented using the open source ADD-Lib in form of an additional DSL for Attribute Based Encryption, with the aim of further enriching the capabilities around the EdgeX platform.","PeriodicalId":114039,"journal":{"name":"2021 Forum on specification & Design Languages (FDL)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124034585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-08DOI: 10.1109/FDL53530.2021.9568377
Mehran Goli, R. Drechsler
The emergence of Virtual Prototypes (VPs) at the Electronic System Level (ESL) has played a major role in modernizing the System-on-Chips (SoCs) design flow to raise design productivity and reduce time-to-market constraint. Leveraging VPs and extending their use-cases for early security validation are shown as a promising direction. As the cost of fixing any security flaws increases with the stage of development, VP-based security validation can significantly avoid costly iterations. In this paper, we propose VIP-VP, a novel VP-based dynamic information flow analysis approach at the ESL.VIP-VP enables designers to validate the information flow policies of a given VP-based SoC against security threat models, such as information leakage (confidentiality) and unauthorized access to data in a memory (integrity). Experimental results including a real-world VP-based SoC demonstrate the scalability and applicability of the proposed approach.
{"title":"VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes","authors":"Mehran Goli, R. Drechsler","doi":"10.1109/FDL53530.2021.9568377","DOIUrl":"https://doi.org/10.1109/FDL53530.2021.9568377","url":null,"abstract":"The emergence of Virtual Prototypes (VPs) at the Electronic System Level (ESL) has played a major role in modernizing the System-on-Chips (SoCs) design flow to raise design productivity and reduce time-to-market constraint. Leveraging VPs and extending their use-cases for early security validation are shown as a promising direction. As the cost of fixing any security flaws increases with the stage of development, VP-based security validation can significantly avoid costly iterations. In this paper, we propose VIP-VP, a novel VP-based dynamic information flow analysis approach at the ESL.VIP-VP enables designers to validate the information flow policies of a given VP-based SoC against security threat models, such as information leakage (confidentiality) and unauthorized access to data in a memory (integrity). Experimental results including a real-world VP-based SoC demonstrate the scalability and applicability of the proposed approach.","PeriodicalId":114039,"journal":{"name":"2021 Forum on specification & Design Languages (FDL)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122266190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-08DOI: 10.1109/FDL53530.2021.9568375
Daniel Lucas, Alexander Schulz-Rosengarten, R. V. Hanxleden, Friedrich Gretz, Franz-Josef Grosch
Software visualization tools can improve the software development process by providing a graphical overview of source code and enhancing collaboration. We here propose a concept to automatically extract mode diagrams from Blech code, an imperative synchronous programming language for embedded, reactive and safety-critical systems. Our main findings are that the visualization is helpful to understand the stateful nature of the source code and that it can enhance the collaboration between developers. It is also found, however, that a good understanding of the precise diagram semantics meaning of the diagram elements is key. Lastly, the findings indicate that preference on different labeling options is highly subjective.
{"title":"Extracting Mode Diagrams from Blech Code","authors":"Daniel Lucas, Alexander Schulz-Rosengarten, R. V. Hanxleden, Friedrich Gretz, Franz-Josef Grosch","doi":"10.1109/FDL53530.2021.9568375","DOIUrl":"https://doi.org/10.1109/FDL53530.2021.9568375","url":null,"abstract":"Software visualization tools can improve the software development process by providing a graphical overview of source code and enhancing collaboration. We here propose a concept to automatically extract mode diagrams from Blech code, an imperative synchronous programming language for embedded, reactive and safety-critical systems. Our main findings are that the visualization is helpful to understand the stateful nature of the source code and that it can enhance the collaboration between developers. It is also found, however, that a good understanding of the precise diagram semantics meaning of the diagram elements is key. Lastly, the findings indicate that preference on different labeling options is highly subjective.","PeriodicalId":114039,"journal":{"name":"2021 Forum on specification & Design Languages (FDL)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134362989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-08DOI: 10.1109/FDL53530.2021.9568381
V. Grimblatt
The world population is growing, and it is estimated that 9.2 billion people will populate the planet by 2050 consuming twice the planet resources yearly. According to Food and Agriculture Organization of the United Nations (FAO), current agricultural production needs to increase by 70% to be able to feed the whole population. On the other hand, four out of nine planetary boundaries are affected by the agriculture. So, the main dilemma is how to produce more food in a sustainable way. In this paper the main agricultural challenges and how the technology, especially IoT, could help to improve the productivity while keeping the planetary boundaries in reasonable values will be presented. Also, an overview of the parameters influencing the growth of crops will be included indicating the suitable values and how they can be monitored and controlled using electronics systems. Additionally, an IoT system being designed is sketched.
{"title":"The Challenge of Agriculture: Increase the Productivity in a Sustainable Way","authors":"V. Grimblatt","doi":"10.1109/FDL53530.2021.9568381","DOIUrl":"https://doi.org/10.1109/FDL53530.2021.9568381","url":null,"abstract":"The world population is growing, and it is estimated that 9.2 billion people will populate the planet by 2050 consuming twice the planet resources yearly. According to Food and Agriculture Organization of the United Nations (FAO), current agricultural production needs to increase by 70% to be able to feed the whole population. On the other hand, four out of nine planetary boundaries are affected by the agriculture. So, the main dilemma is how to produce more food in a sustainable way. In this paper the main agricultural challenges and how the technology, especially IoT, could help to improve the productivity while keeping the planetary boundaries in reasonable values will be presented. Also, an overview of the parameters influencing the growth of crops will be included indicating the suitable values and how they can be monitored and controlled using electronics systems. Additionally, an IoT system being designed is sketched.","PeriodicalId":114039,"journal":{"name":"2021 Forum on specification & Design Languages (FDL)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114666066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-08DOI: 10.1109/FDL53530.2021.9568385
E. Arasteh, R. Dömer
For effective embedded system design, transaction level modeling (TLM) must explicitly expose any available parallelism in the application. Traditional TLM in SystemC utilizes channels for communication and synchronization between concurrent modules, whereas modern TLM-2.0 emphasizes address-accurate communication via explicit interconnect and memories. In both modeling styles, the choice of synchronization mechanisms has a significant impact on the available parallelism in the model which can be exploited by parallel discrete event simulation (PDES). In this work, we propose and analyze a set of non-invasive standard-compliant modeling techniques to increase parallelism in IEEE SystemC TLM-1 and TLM-2.0 models. We measure the performance of aggressive out-of-order PDES in the Recoding Infrastructure for SystemC (RISC) and analyze the parallelism in the models. Our case study on six modeling styles of a state-of-art deep neural network (DNN), namely the GoogLeNet image classification algorithm, demonstrates the impact of varying synchronization mechanisms with simulator run time reduced by 38% compared to a synchronous parallel reference model on a 16-core host machine. Our study also suggests that increased parallel simulation performance indicates better models with higher amounts of parallelism exposed.
为了有效地进行嵌入式系统设计，事务级建模(TLM)必须显式地公开应用程序中任何可用的并行性。SystemC中的传统TLM利用通道在并发模块之间进行通信和同步，而现代TLM-2.0强调通过显式互连和存储器进行地址精确通信。在这两种建模风格中，同步机制的选择对模型中的可用并行性有重大影响，并行离散事件仿真(PDES)可以利用这些并行性。在这项工作中，我们提出并分析了一套非侵入性的标准兼容建模技术，以增加IEEE SystemC TLM-1和TLM-2.0模型的并行性。我们在RISC (Recoding Infrastructure for SystemC)中测量了主动乱序PDES的性能，并分析了模型的并行性。我们对最先进的深度神经网络(DNN)的六种建模风格(即GoogLeNet图像分类算法)的案例研究表明，与16核主机上的同步并行参考模型相比，不同同步机制对模拟器运行时间的影响减少了38%。我们的研究还表明，增加的并行模拟性能表明了更高的并行性暴露的更好的模型。
{"title":"Improving Parallelism in System Level Models by Assessing PDES Performance","authors":"E. Arasteh, R. Dömer","doi":"10.1109/FDL53530.2021.9568385","DOIUrl":"https://doi.org/10.1109/FDL53530.2021.9568385","url":null,"abstract":"For effective embedded system design, transaction level modeling (TLM) must explicitly expose any available parallelism in the application. Traditional TLM in SystemC utilizes channels for communication and synchronization between concurrent modules, whereas modern TLM-2.0 emphasizes address-accurate communication via explicit interconnect and memories. In both modeling styles, the choice of synchronization mechanisms has a significant impact on the available parallelism in the model which can be exploited by parallel discrete event simulation (PDES). In this work, we propose and analyze a set of non-invasive standard-compliant modeling techniques to increase parallelism in IEEE SystemC TLM-1 and TLM-2.0 models. We measure the performance of aggressive out-of-order PDES in the Recoding Infrastructure for SystemC (RISC) and analyze the parallelism in the models. Our case study on six modeling styles of a state-of-art deep neural network (DNN), namely the GoogLeNet image classification algorithm, demonstrates the impact of varying synchronization mechanisms with simulator run time reduced by 38% compared to a synchronous parallel reference model on a 16-core host machine. Our study also suggests that increased parallel simulation performance indicates better models with higher amounts of parallelism exposed.","PeriodicalId":114039,"journal":{"name":"2021 Forum on specification & Design Languages (FDL)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132428222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-08DOI: 10.1109/FDL53530.2021.9568387
Sallar Ahmadi-Pour, V. Herdt, R. Drechsler
Recently, Virtual Prototypes (VPs) implemented in SystemC TLM (Transaction-Level Modeling) have been introduced into the growing RISC-V ecosystem to facilitate early software development and testing. However, accurate environment modeling, which is crucial for Cyber-Physical Systems (CPS), has been mostly neglected to this point. Thus, in this paper, we propose the RISC-V AMS VP framework, that combines an existing open source RISC-V VP with the SystemC AMS (Analog/Mixed Signal) environment modeling style to obtain a RISC-V evaluation platform tailored for CPS. As a case study we created a temperature control system that integrates a sensor and heater component together with a control software. Moreover, we present results on an exemplary fault-injection evaluation that is enabled by bringing together software, hardware and environment models in our unified RISC-V AMS VP framework. Finally, we provide the RISC-V AMS VP framework together with the temperature control system as open source to stimulate further research and as foundation for educational purposes.
{"title":"RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems","authors":"Sallar Ahmadi-Pour, V. Herdt, R. Drechsler","doi":"10.1109/FDL53530.2021.9568387","DOIUrl":"https://doi.org/10.1109/FDL53530.2021.9568387","url":null,"abstract":"Recently, Virtual Prototypes (VPs) implemented in SystemC TLM (Transaction-Level Modeling) have been introduced into the growing RISC-V ecosystem to facilitate early software development and testing. However, accurate environment modeling, which is crucial for Cyber-Physical Systems (CPS), has been mostly neglected to this point. Thus, in this paper, we propose the RISC-V AMS VP framework, that combines an existing open source RISC-V VP with the SystemC AMS (Analog/Mixed Signal) environment modeling style to obtain a RISC-V evaluation platform tailored for CPS. As a case study we created a temperature control system that integrates a sensor and heater component together with a control software. Moreover, we present results on an exemplary fault-injection evaluation that is enabled by bringing together software, hardware and environment models in our unified RISC-V AMS VP framework. Finally, we provide the RISC-V AMS VP framework together with the temperature control system as open source to stimulate further research and as foundation for educational purposes.","PeriodicalId":114039,"journal":{"name":"2021 Forum on specification & Design Languages (FDL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125782334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-08DOI: 10.1109/FDL53530.2021.9568384
Sören Tempel, V. Herdt, R. Drechsler
Constrained IoT devices with limited computing resources are on the rise. They utilize low-end multithreaded operating systems (e.g. RIOT) where each thread is assigned a fixed stack size during the development process. In this regard, it is important to choose an appropriate stack size which does not cause stack overflows and at the same time does not waste scarce memory resources by overestimating the required thread stack size. In this paper we propose an in-vivo technique for stack overflow detection and stack size estimation that leverages Virtual Prototypes (VPs) and is specifically tailored for low-end multithreaded IoT operating systems. We focus on SystemC-based VPs which operate on the TLM abstraction level. VPs are an industrial proven modeling standard to enable early software development and testing. We propose a non-intrusive extension for existing VPs which allows detecting stack overflows and provides a stack size estimation, which is beneficial to a VP-based development process. Our analysis works in-vivo, hence no modification of the executed software binary is required between testing and deployment. Our evaluation using the RIOT operating system revealed two previously unknown stack overflows in RIOT and identified potential stack size overestimation.
{"title":"In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes","authors":"Sören Tempel, V. Herdt, R. Drechsler","doi":"10.1109/FDL53530.2021.9568384","DOIUrl":"https://doi.org/10.1109/FDL53530.2021.9568384","url":null,"abstract":"Constrained IoT devices with limited computing resources are on the rise. They utilize low-end multithreaded operating systems (e.g. RIOT) where each thread is assigned a fixed stack size during the development process. In this regard, it is important to choose an appropriate stack size which does not cause stack overflows and at the same time does not waste scarce memory resources by overestimating the required thread stack size. In this paper we propose an in-vivo technique for stack overflow detection and stack size estimation that leverages Virtual Prototypes (VPs) and is specifically tailored for low-end multithreaded IoT operating systems. We focus on SystemC-based VPs which operate on the TLM abstraction level. VPs are an industrial proven modeling standard to enable early software development and testing. We propose a non-intrusive extension for existing VPs which allows detecting stack overflows and provides a stack size estimation, which is beneficial to a VP-based development process. Our analysis works in-vivo, hence no modification of the executed software binary is required between testing and deployment. Our evaluation using the RIOT operating system revealed two previously unknown stack overflows in RIOT and identified potential stack size overestimation.","PeriodicalId":114039,"journal":{"name":"2021 Forum on specification & Design Languages (FDL)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121677892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-08DOI: 10.1109/FDL53530.2021.9568374
Javier Merino, Raul Gomez, H. Posadas, E. Villar
Smart Robots are an integral part of the 4th Industrial Revolution. Its integration as essential components in robot-based services is not straightforward. Each robot is a cyber-physical system (CPS) where a mechanical part operates under the control of a digital board(s). Modeling and simulation of such devices has specificities to be taken into account. Model-Driven Design (MDD) has proven to be a powerful System Engineering methodology able to cope with the complexity of services built as a system of CPSs (CPSoS). In this paper, a methodology is proposed to seamlessly integrate robots into a MDD framework so that the whole service can be simulated and its performance, analyzed. Although the methodology is valid for robots in general, it has been assessed on a drone-based service.
{"title":"Modeling and Performance Estimation of Robotic Systems using ROS: Application to drone-based Services","authors":"Javier Merino, Raul Gomez, H. Posadas, E. Villar","doi":"10.1109/FDL53530.2021.9568374","DOIUrl":"https://doi.org/10.1109/FDL53530.2021.9568374","url":null,"abstract":"Smart Robots are an integral part of the 4th Industrial Revolution. Its integration as essential components in robot-based services is not straightforward. Each robot is a cyber-physical system (CPS) where a mechanical part operates under the control of a digital board(s). Modeling and simulation of such devices has specificities to be taken into account. Model-Driven Design (MDD) has proven to be a powerful System Engineering methodology able to cope with the complexity of services built as a system of CPSs (CPSoS). In this paper, a methodology is proposed to seamlessly integrate robots into a MDD framework so that the whole service can be simulated and its performance, analyzed. Although the methodology is valid for robots in general, it has been assessed on a drone-based service.","PeriodicalId":114039,"journal":{"name":"2021 Forum on specification & Design Languages (FDL)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115316837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-08DOI: 10.1109/FDL53530.2021.9568373
J. Aguado, A. Duenas
Synchronous Programming (SP) is a model of computation that supports concurrent thread composition and provides deterministic observable behaviour. A recent theory has extended SP with more and higher level clock-synchronised shared memory data types. The present paper implements this clock-synchronised shared memory (CSM) theory and applies it from a model checking perspective. In the CSM theory, types are equipped with a synchronisation policy prescribing how concurrent calls to its methods must be organised. In a policy-constructive system all access methods of all objects can be scheduled in a policy-conformant manner without deadlocking. A policy-constructive system exhibits deterministic behaviour. In our modelling, synchronous policies get codified as never-claims in PROMELA allowing the Spin model checker to be used for searching an execution (interleaving) that satisfies the synchronous product of the never-claims. This interleaving, if exists, provides a policy-conformant schedule for the system model. This schedule verifies that the system is policy-constructive meaning that any policy-conformant schedule results in the same deterministic, observable input-output behaviour for the system.
{"title":"Synchronised Shared Memory and Model Checking: A Proof of Concept","authors":"J. Aguado, A. Duenas","doi":"10.1109/FDL53530.2021.9568373","DOIUrl":"https://doi.org/10.1109/FDL53530.2021.9568373","url":null,"abstract":"Synchronous Programming (SP) is a model of computation that supports concurrent thread composition and provides deterministic observable behaviour. A recent theory has extended SP with more and higher level clock-synchronised shared memory data types. The present paper implements this clock-synchronised shared memory (CSM) theory and applies it from a model checking perspective. In the CSM theory, types are equipped with a synchronisation policy prescribing how concurrent calls to its methods must be organised. In a policy-constructive system all access methods of all objects can be scheduled in a policy-conformant manner without deadlocking. A policy-constructive system exhibits deterministic behaviour. In our modelling, synchronous policies get codified as never-claims in PROMELA allowing the Spin model checker to be used for searching an execution (interleaving) that satisfies the synchronous product of the never-claims. This interleaving, if exists, provides a policy-conformant schedule for the system model. This schedule verifies that the system is policy-constructive meaning that any policy-conformant schedule results in the same deterministic, observable input-output behaviour for the system.","PeriodicalId":114039,"journal":{"name":"2021 Forum on specification & Design Languages (FDL)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126771964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-08DOI: 10.1109/FDL53530.2021.9568386
E. Senn, L. Bourdon
Robotic software can exhibit low performances even while running on allegedly powerful multi-core processor platforms. To find why is essential to guarantee the success of a mission. This paper presents an approach to analyze the processing resource demand of a ROS (Robotic Operating System) based robotic application. The AADL (Architecture Analysis and Design Language) language is used to model the application software, the hardware, and the deployment of the software components onto the hardware. The analysis of processor loads, and the checking of MIPS demand against MIPS capacity, is done with the OSATE2 tool, thanks to a few properties of the language. To set up those properties, a rapid profiling of the hardware and of the software components of the application is done, based on common Linux performance counting tools. The final accuracy is good enough to allow for a fast verification of the deployment options, and to help thinking or rethinking the software vs hardware architectures.
{"title":"Introducing CPU load Analysis from AADL Models for ROS applications : a use case","authors":"E. Senn, L. Bourdon","doi":"10.1109/FDL53530.2021.9568386","DOIUrl":"https://doi.org/10.1109/FDL53530.2021.9568386","url":null,"abstract":"Robotic software can exhibit low performances even while running on allegedly powerful multi-core processor platforms. To find why is essential to guarantee the success of a mission. This paper presents an approach to analyze the processing resource demand of a ROS (Robotic Operating System) based robotic application. The AADL (Architecture Analysis and Design Language) language is used to model the application software, the hardware, and the deployment of the software components onto the hardware. The analysis of processor loads, and the checking of MIPS demand against MIPS capacity, is done with the OSATE2 tool, thanks to a few properties of the language. To set up those properties, a rapid profiling of the hardware and of the software components of the application is done, based on common Linux performance counting tools. The final accuracy is good enough to allow for a fast verification of the deployment options, and to help thinking or rethinking the software vs hardware architectures.","PeriodicalId":114039,"journal":{"name":"2021 Forum on specification & Design Languages (FDL)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125800851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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