Flexible Hybrid Electronics (FHE) Parts that are additively manufactured give engineers and designers greater flexibility in geometry, complexity, and variety or customizability. In this work, UV curable dielectric materials for additive electronics and incorporated Carbon Nano Tubes (CNTs) within a formulated UV/LED curable matrix was used. It will be shown that inkjet printing CNT mixture in specific manner with a commercial UV curable dielectric improves mechanical and thermal properties of the final dielectric compared to the dielectric without the CNT mixture, including a significant decrease in the coefficient of thermal expansion, while keeping excellent electrical properties.
{"title":"A Novel Method of Incorporating CNT into Additive Manufacturing Electronics Dielectric Material","authors":"Daniel Slep, Fan Yang","doi":"10.37665/5ng0w157","DOIUrl":"https://doi.org/10.37665/5ng0w157","url":null,"abstract":"Flexible Hybrid Electronics (FHE) Parts that are additively manufactured give engineers and designers greater flexibility in geometry, complexity, and variety or customizability. In this work, UV curable dielectric materials for additive electronics and incorporated Carbon Nano Tubes (CNTs) within a formulated UV/LED curable matrix was used. It will be shown that inkjet printing CNT mixture in specific manner with a commercial UV curable dielectric improves mechanical and thermal properties of the final dielectric compared to the dielectric without the CNT mixture, including a significant decrease in the coefficient of thermal expansion, while keeping excellent electrical properties.","PeriodicalId":118222,"journal":{"name":"Journal of Surface Mount Technology","volume":"23 5","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141644030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Panahi, A. Hanson, D. Maddipatla, S. Masihi, B. Narakathu, B. Bazuin, Scott Miller, M. Atashbar
A comparative study is presented between two advanced flexible hybrid electronics (FHE) systems designed for monitoring temperature within storage containers across various industries, including food, pharmaceuticals, agriculture, automotive, and defense. The first system, a copper-flex system (CFS), employs an 88.9 µm polyimide substrate with 35 µm thick copper traces, coated with a 12.5 µm polyimide solder mask. The second system, a printed-flex system (PFS), utilizes a 127 µm polyimide substrate with high-temperature resistance and tensile strength. Conductive silver ink was screen-printed on the PFS substrate, and electronic components including a temperature sensor were attached. Functional and reliability tests were performed to check the accuracy and durability of the temperature sensor. Further, environmental and mechanical characterizations including moisture and insulation resistance, corrosion, elongation, bending, and terminal bond strength tests were performed based on ASTM and IPC-TM650 standards. Moisture and insulation resistance test on the PFS test coupons without a coating layer indicated stable resistance of approximately 18 MΩ, while permanent color change indicated oxidation of copper on uncoated CFS test coupons. After 72 hours of corrosion test, both the CFS and PFS “meander line” test coupons covered with polyimide showed negligible change in weight and resistance, approximately 0.35%. A Young’s modulus of 7.17 GPa and 2.6 GPa was calculated from the elongation test for the CFS and PFS, respectively. Bending tests on PFS revealed negligible average resistance change (0.1%) during 180° bending cycles, while no impact was recorded on the CFS. During the terminal bond strength test, soldered wires detached from the CFS test coupons at an average force of 43 N, while it was 3.8 N on the PFS test coupons. Both systems with polyimide coating layer demonstrate robustness and reliability for diverse applications in various industries.
{"title":"Condition Monitoring System: A Flexible Hybrid Electronics Approach for Sealed Container Applications","authors":"M. Panahi, A. Hanson, D. Maddipatla, S. Masihi, B. Narakathu, B. Bazuin, Scott Miller, M. Atashbar","doi":"10.37665/631d5y77","DOIUrl":"https://doi.org/10.37665/631d5y77","url":null,"abstract":"A comparative study is presented between two advanced flexible hybrid electronics (FHE) systems designed for monitoring temperature within storage containers across various industries, including food, pharmaceuticals, agriculture, automotive, and defense. The first system, a copper-flex system (CFS), employs an 88.9 µm polyimide substrate with 35 µm thick copper traces, coated with a 12.5 µm polyimide solder mask. The second system, a printed-flex system (PFS), utilizes a 127 µm polyimide substrate with high-temperature resistance and tensile strength. Conductive silver ink was screen-printed on the PFS substrate, and electronic components including a temperature sensor were attached. Functional and reliability tests were performed to check the accuracy and durability of the temperature sensor. Further, environmental and mechanical characterizations including moisture and insulation resistance, corrosion, elongation, bending, and terminal bond strength tests were performed based on ASTM and IPC-TM650 standards. Moisture and insulation resistance test on the PFS test coupons without a coating layer indicated stable resistance of approximately 18 MΩ, while permanent color change indicated oxidation of copper on uncoated CFS test coupons. After 72 hours of corrosion test, both the CFS and PFS “meander line” test coupons covered with polyimide showed negligible change in weight and resistance, approximately 0.35%. A Young’s modulus of 7.17 GPa and 2.6 GPa was calculated from the elongation test for the CFS and PFS, respectively. Bending tests on PFS revealed negligible average resistance change (0.1%) during 180° bending cycles, while no impact was recorded on the CFS. During the terminal bond strength test, soldered wires detached from the CFS test coupons at an average force of 43 N, while it was 3.8 N on the PFS test coupons. Both systems with polyimide coating layer demonstrate robustness and reliability for diverse applications in various industries.","PeriodicalId":118222,"journal":{"name":"Journal of Surface Mount Technology","volume":"23 8","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141644027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Intermetallic compounds (IMC) or intermediate phases are formed between two or more metallic elements in many metal alloy systems. During soldering, an IMC is formed at the soldered interface as the molten solder reacts with an element in the substrate. IMCs also can form within the bulk solder as the joint solidifies. IMCs have critical roles in the solder joint quality and reliability. Unlike most metal alloys, an intermetallic compound typically has a fixed stoichiometry and is in variance with the conventional phases or constituents in the metal system (e.g., alpha and beta). IMCs have a different crystal structure than any of its constituents and some but never all the characteristics and properties of its constituents. Ductility is an important solder joint property, and the low intrinsic ductility of IMCs is associated with brittle behavior and reliability risk in service. However, a review of published solder field failures shows little evidence that IMC properties or IMC evolution under service conditions reduce solder joint reliability. Most IMC-induced solder joint failures are found to result from incorrect material specification or uncontrolled soldering processes. This paper describes the IMCs that occur typically in eutectic, Sn63Pb37 solder and near-eutectic SAC305 or other tin-based Pb-free solder alloys, including how they impact solder joint reliability. The paper also describes the potential impact of IMCs on the solder joint reliability for the newest generation of Pb-free high-performance solder alloys.
{"title":"Intermetallic Compounds in Solder Alloys: Common Misconceptions","authors":"David Hillman, T. Pearson, Richard Coyle","doi":"10.37665/pmtrnw39","DOIUrl":"https://doi.org/10.37665/pmtrnw39","url":null,"abstract":"Intermetallic compounds (IMC) or intermediate phases are formed between two or more metallic elements in many metal alloy systems. During soldering, an IMC is formed at the soldered interface as the molten solder reacts with an element in the substrate. IMCs also can form within the bulk solder as the joint solidifies. IMCs have critical roles in the solder joint quality and reliability. Unlike most metal alloys, an intermetallic compound typically has a fixed stoichiometry and is in variance with the conventional phases or constituents in the metal system (e.g., alpha and beta). IMCs have a different crystal structure than any of its constituents and some but never all the characteristics and properties of its constituents. Ductility is an important solder joint property, and the low intrinsic ductility of IMCs is associated with brittle behavior and reliability risk in service. However, a review of published solder field failures shows little evidence that IMC properties or IMC evolution under service conditions reduce solder joint reliability. Most IMC-induced solder joint failures are found to result from incorrect material specification or uncontrolled soldering processes. This paper describes the IMCs that occur typically in eutectic, Sn63Pb37 solder and near-eutectic SAC305 or other tin-based Pb-free solder alloys, including how they impact solder joint reliability. The paper also describes the potential impact of IMCs on the solder joint reliability for the newest generation of Pb-free high-performance solder alloys.","PeriodicalId":118222,"journal":{"name":"Journal of Surface Mount Technology","volume":"3 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141640335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Finite element modeling was used to evaluate the effects of thermal pad solder voiding on the thermal resistance of Quad Flatpack No Lead components. This included two different approaches for modeling solder voids: many small, distributed voids, the effects of which were averaged across the entire solder contact area or a single discrete void. Two approaches were used for defining the thermal path established in the solder. The effects of other design parameters - thermal boundary conditions, the presence of thermal vias under the package, and the size of the die power dissipation area – were also addressed. Modeling showed that thermal vias and external boundary conditions had the most significant impact on the package thermal resistance. Solder pad voids and concentrated die-level heat dissipation, for the range used in this study, had noticeable but less significant impacts on thermal resistance. The study also compared different approaches for simulating solder voiding and identified ranges in which modeling simulations are most appropriate.
{"title":"Modeling the Effects of Thermal Pad Voiding on Quad Flatpack No-lead (QFN) Components","authors":"R. Wilcoxon, T. Pearson, D. Hillman","doi":"10.37665/smt.v36i2.37","DOIUrl":"https://doi.org/10.37665/smt.v36i2.37","url":null,"abstract":"Finite element modeling was used to evaluate the effects of thermal pad solder voiding on the thermal resistance of Quad Flatpack No Lead components. This included two different approaches for modeling solder voids: many small, distributed voids, the effects of which were averaged across the entire solder contact area or a single discrete void. Two approaches were used for defining the thermal path established in the solder. The effects of other design parameters - thermal boundary conditions, the presence of thermal vias under the package, and the size of the die power dissipation area – were also addressed. Modeling showed that thermal vias and external boundary conditions had the most significant impact on the package thermal resistance. Solder pad voids and concentrated die-level heat dissipation, for the range used in this study, had noticeable but less significant impacts on thermal resistance. The study also compared different approaches for simulating solder voiding and identified ranges in which modeling simulations are most appropriate.","PeriodicalId":118222,"journal":{"name":"Journal of Surface Mount Technology","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128994754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Rafanelli, D. Hillman, C. Johnson, R. Coyle, T. Pearson
The Aerospace & Defense (A & D) industries maintain a high level of interest in the expansive amount of work performed in developing and qualifying Pb-free solder alloys. The three main areas of interest continue to be thermal cycle, mechanical shock, and vibration. The past twenty years have seen an unprecedented increase in alloy development such that the concepts of “generations of solders and “families of solders” have been coined to help manage the numerous individual alloys on the market today. This paper will discuss work done with Pb-free solder alloys, many with the addition of constituents focusing on varying property enhancements. The purpose is to provide a “snap shot” summary of progress to date and relate perspectives both as advantages and concerns solely in a constructive manner to aid researchers in planning their next steps in development and qualification of these alloys.
{"title":"Pb-Free Solders and Aerospace/Defense (A&D) High Performance Considerations","authors":"A. Rafanelli, D. Hillman, C. Johnson, R. Coyle, T. Pearson","doi":"10.37665/smt.v36i2.30","DOIUrl":"https://doi.org/10.37665/smt.v36i2.30","url":null,"abstract":"The Aerospace & Defense (A & D) industries maintain a high level of interest in the expansive amount of work performed in developing and qualifying Pb-free solder alloys. The three main areas of interest continue to be thermal cycle, mechanical shock, and vibration. The past twenty years have seen an unprecedented increase in alloy development such that the concepts of “generations of solders and “families of solders” have been coined to help manage the numerous individual alloys on the market today. This paper will discuss work done with Pb-free solder alloys, many with the addition of constituents focusing on varying property enhancements. The purpose is to provide a “snap shot” summary of progress to date and relate perspectives both as advantages and concerns solely in a constructive manner to aid researchers in planning their next steps in development and qualification of these alloys.","PeriodicalId":118222,"journal":{"name":"Journal of Surface Mount Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130529411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lead-free solder metal alloys can be formed into supercooled liquid metal microcapsules and used to create solid full metal interconnects at dramatically lower processing temperatures. These alloys can be made with or without bismuth. The technology encapsulates known and established RoHS compliant solder alloys inside a thin oxide/organic shell nanofilm that keeps the metal in a metastable supercooled liquid state at ambient temperatures. The thin oxide/organic shell can be mechanically broken or chemically dissolved to release the liquid metal that then rapidly solidifies all without requiring heat. The novel solder interconnect technology avoids thermal damage to components and materials, or quality issues caused by coefficient of thermal expansion mismatch.
{"title":"Lower Temperature Soldering Using Supercooled Liquid Metal","authors":"Ian D. Tevis, D. Paramanik","doi":"10.37665/smt.v36i2.36","DOIUrl":"https://doi.org/10.37665/smt.v36i2.36","url":null,"abstract":"Lead-free solder metal alloys can be formed into supercooled liquid metal microcapsules and used to create solid full metal interconnects at dramatically lower processing temperatures. These alloys can be made with or without bismuth. The technology encapsulates known and established RoHS compliant solder alloys inside a thin oxide/organic shell nanofilm that keeps the metal in a metastable supercooled liquid state at ambient temperatures. The thin oxide/organic shell can be mechanically broken or chemically dissolved to release the liquid metal that then rapidly solidifies all without requiring heat. The novel solder interconnect technology avoids thermal damage to components and materials, or quality issues caused by coefficient of thermal expansion mismatch.","PeriodicalId":118222,"journal":{"name":"Journal of Surface Mount Technology","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127512385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Hillman, T. Pearson, R. Wilcoxon, Grace Cooke, Sue Margheim, Elena Gladen, T. Munson, D. Fritz
The implementation of the Restriction of Hazardous Substances (RoHS) European Union (EU) Directive in 2005 resulted in the introduction of pure tin as an acceptable surface finish for printed circuit boards and component terminations. A drawback of pure tin surface finishes is the potential to form tin whiskers. Tin whiskers are a metallurgical phenomenon that is associated with tin rich/pure tin materials and has been a topic of intense industry interest. The acceptance and usage of pure tin by the electronics industry component fabricators is understandable as the pure tin surface finishes are inexpensive, are simple plating systems to operate and have reasonable solderability characteristics. However, high performance/harsh environment electronics typically have product life cycles that are measured in decades and therefore are much more susceptible to the potential long term threat of tin whiskers. The GEIA-STD-0005-2 “Standard for Mitigating the Effects of Tin Whiskers in Aerospace and High Performance Electronic Systems” established the definition of the term “Pb-free tin” as : “Pb-free Tin is defined to be pure tin or any tin alloy with <3% lead (Pb) content by weight. A functional definition of “pure tin” was necessary so that the electronics industry could establish tin whisker risk protocols against a known acceptable target value in terms of soldering materials and processes. An investigation was conducted to determine the influence of 1% - 5% elemental lead (Pb) content in tin plating on tin whisker initiation and growth. The investigation results were used in the revision of the GEIA-STD-0005-2 “Standard for Mitigating the Effects of Tin Whiskers in Aerospace and High Performance Electronic Systems” specification technical discussions.
{"title":"Influence of Element Lead (Pb) Content in Tin Plating on Tin Whisker Initiation/Growth","authors":"D. Hillman, T. Pearson, R. Wilcoxon, Grace Cooke, Sue Margheim, Elena Gladen, T. Munson, D. Fritz","doi":"10.37665/smt.v36i1.28","DOIUrl":"https://doi.org/10.37665/smt.v36i1.28","url":null,"abstract":"The implementation of the Restriction of Hazardous Substances (RoHS) European Union (EU) Directive in 2005 resulted in the introduction of pure tin as an acceptable surface finish for printed circuit boards and component terminations. A drawback of pure tin surface finishes is the potential to form tin whiskers. Tin whiskers are a metallurgical phenomenon that is associated with tin rich/pure tin materials and has been a topic of intense industry interest. The acceptance and usage of pure tin by the electronics industry component fabricators is understandable as the pure tin surface finishes are inexpensive, are simple plating systems to operate and have reasonable solderability characteristics. However, high performance/harsh environment electronics typically have product life cycles that are measured in decades and therefore are much more susceptible to the potential long term threat of tin whiskers. The GEIA-STD-0005-2 “Standard for Mitigating the Effects of Tin Whiskers in Aerospace and High Performance Electronic Systems” established the definition of the term “Pb-free tin” as : “Pb-free Tin is defined to be pure tin or any tin alloy with <3% lead (Pb) content by weight. A functional definition of “pure tin” was necessary so that the electronics industry could establish tin whisker risk protocols against a known acceptable target value in terms of soldering materials and processes. An investigation was conducted to determine the influence of 1% - 5% elemental lead (Pb) content in tin plating on tin whisker initiation and growth. The investigation results were used in the revision of the GEIA-STD-0005-2 “Standard for Mitigating the Effects of Tin Whiskers in Aerospace and High Performance Electronic Systems” specification technical discussions.","PeriodicalId":118222,"journal":{"name":"Journal of Surface Mount Technology","volume":"480 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133632087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
James Feng, B. Germann, A. Ramm, F. Herrault, John R. Hamre
As millimeter wave RF device applications expand above traditional microwave frequency bands in the global communications, automotive and Mil-Aero markets, the need to limit interconnect signal losses related to parasitic elements has never been more important. As the frequency increases, device designers are facing numerous challenges, complications, and costs when fabricating interconnects with techniques such as copper pillar bumps, wire, ribbon or wedge bonding in 3DIC packaging. Printing conformal interconnects with Aerosol Jet® direct-write technology can offer package designers and RF engineers a new approach for optimizing interconnect transitions to active die, tailoring the loss characteristics to specific application requirements and eliminating the need to compensate for high signal transmission losses. Printed interconnects can be digitally designed into the package with a variety of metallic and dielectric materials. As these interconnects are conformally printed on the 3D surface of the package, the trace length can be minimized with zero loop height, reducing parasitic inductance to active die circuitry specifically for die on board, die in trench, or die on die with pads-up packaging configurations. In this work, Aerosol Jet® printed interconnects with silver nanoparticle inks are compared with the gold microstrip transmission lines as well as traditional gold bond wires, for performance up to 110 GHz. We will share examples showcasing that the printed interconnects can have similar RF transmission performance to microstrip, with significantly lower loss than bondwires especially at high frequencies. We will also discuss design effects for Aerosol Jet® printed RF interconnects up to 110 GHz based on a set of results for different line heights with a given line width printed with a silver ink.
{"title":"Aerosol Jet Printed Interconnects for Millimeter-Wave Components","authors":"James Feng, B. Germann, A. Ramm, F. Herrault, John R. Hamre","doi":"10.37665/smt.v36i1.35","DOIUrl":"https://doi.org/10.37665/smt.v36i1.35","url":null,"abstract":"As millimeter wave RF device applications expand above traditional microwave frequency bands in the global communications, automotive and Mil-Aero markets, the need to limit interconnect signal losses related to parasitic elements has never been more important. As the frequency increases, device designers are facing numerous challenges, complications, and costs when fabricating interconnects with techniques such as copper pillar bumps, wire, ribbon or wedge bonding in 3DIC packaging. Printing conformal interconnects with Aerosol Jet® direct-write technology can offer package designers and RF engineers a new approach for optimizing interconnect transitions to active die, tailoring the loss characteristics to specific application requirements and eliminating the need to compensate for high signal transmission losses. Printed interconnects can be digitally designed into the package with a variety of metallic and dielectric materials. As these interconnects are conformally printed on the 3D surface of the package, the trace length can be minimized with zero loop height, reducing parasitic inductance to active die circuitry specifically for die on board, die in trench, or die on die with pads-up packaging configurations. In this work, Aerosol Jet® printed interconnects with silver nanoparticle inks are compared with the gold microstrip transmission lines as well as traditional gold bond wires, for performance up to 110 GHz. We will share examples showcasing that the printed interconnects can have similar RF transmission performance to microstrip, with significantly lower loss than bondwires especially at high frequencies. We will also discuss design effects for Aerosol Jet® printed RF interconnects up to 110 GHz based on a set of results for different line heights with a given line width printed with a silver ink.","PeriodicalId":118222,"journal":{"name":"Journal of Surface Mount Technology","volume":"23 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132726693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Static bending-induced solder joints damage is a main reliability concern for aerospace and military industries whose Printed Circuit Board Assemblies (PCBAs) are required to remain functional under flexural loading. In order to dissipate heat in an equipment, it is common to install thermal gap pads on electronic packages. When compressing thermal gap pads during the fixture process, the PCBA can bend and solder joints can therefore crack if the deflection is too important. This paper reports the durability of 96.5Sn-3.0Ag-0.5Cu (SAC305) and 62Sn-36Pb-2Ag (SnPb36Ag2) Ball Grid Array (BGA) assemblies under static flexural loading at -55°C, 20°C and 125°C. As electronic equipment can be stored at high temperature for prolonged durations, some SAC305 test vehicles were also aged at 125°C for 192 hours. For each test configuration, the bending tests were conducted at a ramp-rate of 2 mm/min and the central displacement-to-failure was measured. Finite Element Modeling (FEM) analysis was conducted considering a global-local approach and the transfer function between the central displacement-to-failure and the local PCB strain near the critical solder joints was determined for each test configuration. The results give the necessary data for designers to assess whether a specific PCBA design subjected to static bending is at risk or not.
{"title":"Mechanical Characterization of SAC305 and SnPb36Ag2 BGA Assemblies Under Static Flexural Loading","authors":"J. Libot, O. Dalverny, J. Alexis, Jeremy Bosq","doi":"10.37665/smt.v36i1.34","DOIUrl":"https://doi.org/10.37665/smt.v36i1.34","url":null,"abstract":"Static bending-induced solder joints damage is a main reliability concern for aerospace and military industries whose Printed Circuit Board Assemblies (PCBAs) are required to remain functional under flexural loading. In order to dissipate heat in an equipment, it is common to install thermal gap pads on electronic packages. When compressing thermal gap pads during the fixture process, the PCBA can bend and solder joints can therefore crack if the deflection is too important. This paper reports the durability of 96.5Sn-3.0Ag-0.5Cu (SAC305) and 62Sn-36Pb-2Ag (SnPb36Ag2) Ball Grid Array (BGA) assemblies under static flexural loading at -55°C, 20°C and 125°C. As electronic equipment can be stored at high temperature for prolonged durations, some SAC305 test vehicles were also aged at 125°C for 192 hours. For each test configuration, the bending tests were conducted at a ramp-rate of 2 mm/min and the central displacement-to-failure was measured. Finite Element Modeling (FEM) analysis was conducted considering a global-local approach and the transfer function between the central displacement-to-failure and the local PCB strain near the critical solder joints was determined for each test configuration. The results give the necessary data for designers to assess whether a specific PCBA design subjected to static bending is at risk or not.","PeriodicalId":118222,"journal":{"name":"Journal of Surface Mount Technology","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128536851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SIR is a recognised tool for establishing electrochemical reliability of electronic assemblies. Currently the test patterns in the standards reflect coarse pitch components. An intercomparison has been completed with the aim of establishing the introduction of a fine pitch SIR pattern with a 200µm gap. This exercise included the contribution from seven international participants. This new pattern moves the test method forward into the realm of current technologies where components of this pitch are common place. The study reported here validates the basis for the introduction of the new pattern, and confirms acceptable Gauge R&R for the SIR technique. The analysis also highlights the challenges in controlling humidity to achieve comparable results between different users. The results also point to the challenges in achieving acceptable Gauge R&R when measuring resistances >1011Ω.
{"title":"A Gauge Study of an Intercomparison Evaluation to Implement the use of Fine-Pitch Test Patterns for Surface Insulation Resistance (SIR) Testing of Solder Fluxes","authors":"C. Hunt","doi":"10.37665/smt.v35i1.24","DOIUrl":"https://doi.org/10.37665/smt.v35i1.24","url":null,"abstract":"SIR is a recognised tool for establishing electrochemical reliability of electronic assemblies. Currently the test patterns in the standards reflect coarse pitch components. An intercomparison has been completed with the aim of establishing the introduction of a fine pitch SIR pattern with a 200µm gap. This exercise included the contribution from seven international participants. This new pattern moves the test method forward into the realm of current technologies where components of this pitch are common place. The study reported here validates the basis for the introduction of the new pattern, and confirms acceptable Gauge R&R for the SIR technique. The analysis also highlights the challenges in controlling humidity to achieve comparable results between different users. The results also point to the challenges in achieving acceptable Gauge R&R when measuring resistances >1011Ω.","PeriodicalId":118222,"journal":{"name":"Journal of Surface Mount Technology","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130896314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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