Pub Date : 2012-07-16DOI: 10.1109/SAMOS.2012.6404199
Dip Goswami, Reinhard Schneider, Alejandro Masrur, M. Lukasiewycz, S. Chakraborty, Harald Voit, A. Annaswamy
Systems with tightly interacting computational (cyber) units and physical systems are generally referred to as cyber-physical systems. They involve an interplay between embedded systems, control theory, real-time systems and software engineering. A very good example of cyber-physical systems design arises in the context of automotive architectures and software. Modern high-end cars have 50-100 processors or electronic control units (ECUs) that communicate over a network of buses such as CAN and FlexRay. In such complex settings, traditional control-theoretic approaches - where control engineers are only concerned with high-level plant and controller models - start breaking down. This is because implementation-level realities such as message delay, jitter, and task execution times are not adequately considered when designing the controller. Hence, it is becoming necessary to adopt a more holistic, cyber-physical systems design approach where the semantic gap between high-level control models and their actual implementations on multiprocessor automotive platforms is quantified and consciously closed. In this paper we give several examples on how this may be done and the current research challenges in this area that are being faced by the academia and the industry.
{"title":"Challenges in automotive cyber-physical systems design","authors":"Dip Goswami, Reinhard Schneider, Alejandro Masrur, M. Lukasiewycz, S. Chakraborty, Harald Voit, A. Annaswamy","doi":"10.1109/SAMOS.2012.6404199","DOIUrl":"https://doi.org/10.1109/SAMOS.2012.6404199","url":null,"abstract":"Systems with tightly interacting computational (cyber) units and physical systems are generally referred to as cyber-physical systems. They involve an interplay between embedded systems, control theory, real-time systems and software engineering. A very good example of cyber-physical systems design arises in the context of automotive architectures and software. Modern high-end cars have 50-100 processors or electronic control units (ECUs) that communicate over a network of buses such as CAN and FlexRay. In such complex settings, traditional control-theoretic approaches - where control engineers are only concerned with high-level plant and controller models - start breaking down. This is because implementation-level realities such as message delay, jitter, and task execution times are not adequately considered when designing the controller. Hence, it is becoming necessary to adopt a more holistic, cyber-physical systems design approach where the semantic gap between high-level control models and their actual implementations on multiprocessor automotive platforms is quantified and consciously closed. In this paper we give several examples on how this may be done and the current research challenges in this area that are being faced by the academia and the industry.","PeriodicalId":130275,"journal":{"name":"2012 International Conference on Embedded Computer Systems (SAMOS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126278295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-16DOI: 10.1109/SAMOS.2012.6404160
G. Keramidas, Chrysovalantis Datsios, S. Kaxiras
We present a novel framework to dynamically reconfigure on-chip memory resources according to the changing behavior of the running applications. Our framework enables smooth scaling (i.e., resizing) of the on-chip caches targeting both performance and power efficiency. In contrast to previous approaches, the resizing decisions in our framework are not tainted by transient events (e.g., misses) that are due to downsizing avoiding at the same time swinging the cache size due to trial-and-error resizing decisions. This minimizes both execution time penalty induced by resizing as well as the effective cache size. Furthermore, an inherent property of our approach is that the actual invalidation of the cache blocks and the corresponding write-backs of the dirty blocks are asynchronous to resizing decisions, ensuring a smooth transition from one size to another. This makes it possible to apply our framework even on write-back caches. The proposed mechanism is simple to implement requiring minimal additional hardware. Using cycle-accurate simulations, we evaluate our proposal against previously proposed techniques. In all cases, our experimental results show significant benefits in both power and performance.
{"title":"A framework for efficient cache resizing","authors":"G. Keramidas, Chrysovalantis Datsios, S. Kaxiras","doi":"10.1109/SAMOS.2012.6404160","DOIUrl":"https://doi.org/10.1109/SAMOS.2012.6404160","url":null,"abstract":"We present a novel framework to dynamically reconfigure on-chip memory resources according to the changing behavior of the running applications. Our framework enables smooth scaling (i.e., resizing) of the on-chip caches targeting both performance and power efficiency. In contrast to previous approaches, the resizing decisions in our framework are not tainted by transient events (e.g., misses) that are due to downsizing avoiding at the same time swinging the cache size due to trial-and-error resizing decisions. This minimizes both execution time penalty induced by resizing as well as the effective cache size. Furthermore, an inherent property of our approach is that the actual invalidation of the cache blocks and the corresponding write-backs of the dirty blocks are asynchronous to resizing decisions, ensuring a smooth transition from one size to another. This makes it possible to apply our framework even on write-back caches. The proposed mechanism is simple to implement requiring minimal additional hardware. Using cycle-accurate simulations, we evaluate our proposal against previously proposed techniques. In all cases, our experimental results show significant benefits in both power and performance.","PeriodicalId":130275,"journal":{"name":"2012 International Conference on Embedded Computer Systems (SAMOS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130711526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-16DOI: 10.1109/SAMOS.2012.6404200
M. Glaß, J. Teich, Liyuan Zhang
Control applications have become an integral part of modern networked embedded systems. However, there often exists a gap between control engineering and system design. The control engineer has detailed knowledge about the algorithms but is abstracting from the system architecture and implementation. On the other hand, the system designer aims at achieving high-quality implementations based on quality constraints specified by the control engineer. This may result in either an overdesigned system in case the specifications are pessimistic or an unsafe system behavior when specifications are too optimistic. Thus, future design automation approaches have to consider the quality of control applications both as design objectives and design constraints to achieve safe yet highly optimized system implementations. The work at hand introduces an automatic tool flow at the Electronic System Level (ESL) that enables the optimization of a system implementation with quality of control being introduced as a principal design objective, like the maximum braking distance, while respecting constraints like maximum slip to ensure maneuverability of a car. The gap between mathematically well-defined models for system synthesis and common analysis techniques for control quality is bridged by co-simulation: A SystemC-based virtual prototype of a distributed controller implementation is combined with high-level models of the plants specified in Matlab/Simulink. Through a model transformation, the traditional development process of control applications is combined with state-of-the-art ESL techniques, ensuring model consistency while enabling a high degree of automation.
{"title":"A co-simulation approach for system-level analysis of embedded control systems","authors":"M. Glaß, J. Teich, Liyuan Zhang","doi":"10.1109/SAMOS.2012.6404200","DOIUrl":"https://doi.org/10.1109/SAMOS.2012.6404200","url":null,"abstract":"Control applications have become an integral part of modern networked embedded systems. However, there often exists a gap between control engineering and system design. The control engineer has detailed knowledge about the algorithms but is abstracting from the system architecture and implementation. On the other hand, the system designer aims at achieving high-quality implementations based on quality constraints specified by the control engineer. This may result in either an overdesigned system in case the specifications are pessimistic or an unsafe system behavior when specifications are too optimistic. Thus, future design automation approaches have to consider the quality of control applications both as design objectives and design constraints to achieve safe yet highly optimized system implementations. The work at hand introduces an automatic tool flow at the Electronic System Level (ESL) that enables the optimization of a system implementation with quality of control being introduced as a principal design objective, like the maximum braking distance, while respecting constraints like maximum slip to ensure maneuverability of a car. The gap between mathematically well-defined models for system synthesis and common analysis techniques for control quality is bridged by co-simulation: A SystemC-based virtual prototype of a distributed controller implementation is combined with high-level models of the plants specified in Matlab/Simulink. Through a model transformation, the traditional development process of control applications is combined with state-of-the-art ESL techniques, ensuring model consistency while enabling a high degree of automation.","PeriodicalId":130275,"journal":{"name":"2012 International Conference on Embedded Computer Systems (SAMOS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132850054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-16DOI: 10.1109/SAMOS.2012.6404183
João MP Cardoso, Tiago Carvalho, J. Teixeira, P. Diniz, F. Gonçalves, Z. Petrov
LARA is a programming language being developed to complement application code in a host programming language with instrumentation code, for monitoring, logging, and debugging, user's knowledge about specific characteristics of the application, non-functional requirements, and compiler, mapping and synthesis strategies to guide/control design-flows, especially the ones used to map computations to FPGA-based systems. This paper shows how the aspect-oriented approach provided by LARA allows developers to specify complementary program information that can be used by LARA aware design-flows to promote customized FPGA-based software/hardware implementations. Program and compiler/mapping specialization take advantage of specific properties of applications to optimize and customize specific application modules and software/hardware implementations, e.g., according to usage contexts. We illustrate the concept using a hotspot function from a real-life, industrial, application. The results show the importance of program specialization in deriving hardware/software implementations with higher-performance.
{"title":"Hardware/software specialization through aspects: The LARA approach","authors":"João MP Cardoso, Tiago Carvalho, J. Teixeira, P. Diniz, F. Gonçalves, Z. Petrov","doi":"10.1109/SAMOS.2012.6404183","DOIUrl":"https://doi.org/10.1109/SAMOS.2012.6404183","url":null,"abstract":"LARA is a programming language being developed to complement application code in a host programming language with instrumentation code, for monitoring, logging, and debugging, user's knowledge about specific characteristics of the application, non-functional requirements, and compiler, mapping and synthesis strategies to guide/control design-flows, especially the ones used to map computations to FPGA-based systems. This paper shows how the aspect-oriented approach provided by LARA allows developers to specify complementary program information that can be used by LARA aware design-flows to promote customized FPGA-based software/hardware implementations. Program and compiler/mapping specialization take advantage of specific properties of applications to optimize and customize specific application modules and software/hardware implementations, e.g., according to usage contexts. We illustrate the concept using a hotspot function from a real-life, industrial, application. The results show the importance of program specialization in deriving hardware/software implementations with higher-performance.","PeriodicalId":130275,"journal":{"name":"2012 International Conference on Embedded Computer Systems (SAMOS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133173969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-16DOI: 10.1109/SAMOS.2012.6404187
Filippo Borlenghi, Dominik Auras, E. M. Witte, T. Kempf, G. Ascheid, R. Leupers, H. Meyr
FPGA-based prototyping is nowadays common practice in the functional verification of hardware components since it allows to cover a large number of test cases in a shorter time compared to HDL simulation. In addition, an FPGA-based emulator significantly accelerates the simulation with respect to bit-true software models. This speed-up is crucial when the statistical properties of a system have to be analyzed by Monte Carlo techniques. In this paper we consider a multiple-input multiple-output (MIMO) wireless communication system and show how integrating an FPGA accelerator in the software simulation framework is key to enable the development of complex hardware components in the receiver, from algorithm all the way to chip testing. In particular, we focus on a MIMO detector implementation based on the depth-first sphere decoding algorithm. The speed-up of up to 3 orders of magnitude achieved by hardware-accelerated simulation compared to a pure software testbed enables an extensive fixed-point exploration. Furthermore, it allows a unique characterization of the system communication performance and the MIMO detector run-time characteristics, which vary for different configuration parameters and operating scenarios and hence require a thorough investigation.
{"title":"An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systems","authors":"Filippo Borlenghi, Dominik Auras, E. M. Witte, T. Kempf, G. Ascheid, R. Leupers, H. Meyr","doi":"10.1109/SAMOS.2012.6404187","DOIUrl":"https://doi.org/10.1109/SAMOS.2012.6404187","url":null,"abstract":"FPGA-based prototyping is nowadays common practice in the functional verification of hardware components since it allows to cover a large number of test cases in a shorter time compared to HDL simulation. In addition, an FPGA-based emulator significantly accelerates the simulation with respect to bit-true software models. This speed-up is crucial when the statistical properties of a system have to be analyzed by Monte Carlo techniques. In this paper we consider a multiple-input multiple-output (MIMO) wireless communication system and show how integrating an FPGA accelerator in the software simulation framework is key to enable the development of complex hardware components in the receiver, from algorithm all the way to chip testing. In particular, we focus on a MIMO detector implementation based on the depth-first sphere decoding algorithm. The speed-up of up to 3 orders of magnitude achieved by hardware-accelerated simulation compared to a pure software testbed enables an extensive fixed-point exploration. Furthermore, it allows a unique characterization of the system communication performance and the MIMO detector run-time characteristics, which vary for different configuration parameters and operating scenarios and hence require a thorough investigation.","PeriodicalId":130275,"journal":{"name":"2012 International Conference on Embedded Computer Systems (SAMOS)","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122098487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-16DOI: 10.1109/SAMOS.2012.6404195
P. Marwedel, M. Engel
Computing in cyber-physical systems has to be efficient in terms of a number of objectives. In particular, computing has to be execution-time and energy efficient. In this paper, we will consider optimization techniques aiming at efficiency in terms of these two objectives. In the first part, we will consider techniques for the integration of compilers and worst-case execution time (WCET) estimation. We will demonstrate, how such integration opens the door to WCET-reduction algorithms. For example, an algorithm for WCET-aware compilation reduces the WCET for an automotive application by more than 50% by exploiting scratch pad memories (SPMs). In the second part, we will demonstrate techniques for improving the energy efficiency of cyber-physical systems, in particular the use of SPMs. In the third part, we demonstrate how the optimization for multiple objectives taken into account. This paper provides an overview of work performed at the Chair for Embedded Systems of TU Dortmund and the Informatik Centrum Dortmund, Germany1.
{"title":"Efficient computing in cyber-physical systems","authors":"P. Marwedel, M. Engel","doi":"10.1109/SAMOS.2012.6404195","DOIUrl":"https://doi.org/10.1109/SAMOS.2012.6404195","url":null,"abstract":"Computing in cyber-physical systems has to be efficient in terms of a number of objectives. In particular, computing has to be execution-time and energy efficient. In this paper, we will consider optimization techniques aiming at efficiency in terms of these two objectives. In the first part, we will consider techniques for the integration of compilers and worst-case execution time (WCET) estimation. We will demonstrate, how such integration opens the door to WCET-reduction algorithms. For example, an algorithm for WCET-aware compilation reduces the WCET for an automotive application by more than 50% by exploiting scratch pad memories (SPMs). In the second part, we will demonstrate techniques for improving the energy efficiency of cyber-physical systems, in particular the use of SPMs. In the third part, we demonstrate how the optimization for multiple objectives taken into account. This paper provides an overview of work performed at the Chair for Embedded Systems of TU Dortmund and the Informatik Centrum Dortmund, Germany1.","PeriodicalId":130275,"journal":{"name":"2012 International Conference on Embedded Computer Systems (SAMOS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131827402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-16DOI: 10.1109/SAMOS.2012.6404191
P. Meloni, Sebastiano Pomata, L. Raffo, R. Piscitelli, A. Pimentel
Modern heterogeneous multi-processor embedded systems very often expose to the designer a large number of degrees of freedom, related to the application partitioning/mapping and to the component- and system-level architecture composition. The number is even larger when the designer targets systems based on configurable Application Specific Instruction-set Processors, due to the fine customizability of their internal architecture. This poses the need for effective and user-friendly design tools, capable to deal with the extremely wide system-level design space exposed by multi-processor architecture and, at the same time, with an extended variety of processing element architectural configurations, to be evaluated in detail and in reasonable times. As a possible solution, within the MADNESS project [1], an integrated toolset has been proposed, combining the benefits of novel fast FPGA-based prototyping techniques with those provided by high-level simulation. In the toolset, the resulting evaluation platform serves as an underlying layer for a Design Space search algorithm. The paper presents the individual tools included in the toolset and their interaction strategy. The approach is then evaluated with a design space exploration case study, taking as a target application a video compression kernel. The integrated toolset has been used to produce a Pareto front of evaluated system-level configurations.
{"title":"Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems","authors":"P. Meloni, Sebastiano Pomata, L. Raffo, R. Piscitelli, A. Pimentel","doi":"10.1109/SAMOS.2012.6404191","DOIUrl":"https://doi.org/10.1109/SAMOS.2012.6404191","url":null,"abstract":"Modern heterogeneous multi-processor embedded systems very often expose to the designer a large number of degrees of freedom, related to the application partitioning/mapping and to the component- and system-level architecture composition. The number is even larger when the designer targets systems based on configurable Application Specific Instruction-set Processors, due to the fine customizability of their internal architecture. This poses the need for effective and user-friendly design tools, capable to deal with the extremely wide system-level design space exposed by multi-processor architecture and, at the same time, with an extended variety of processing element architectural configurations, to be evaluated in detail and in reasonable times. As a possible solution, within the MADNESS project [1], an integrated toolset has been proposed, combining the benefits of novel fast FPGA-based prototyping techniques with those provided by high-level simulation. In the toolset, the resulting evaluation platform serves as an underlying layer for a Design Space search algorithm. The paper presents the individual tools included in the toolset and their interaction strategy. The approach is then evaluated with a design space exploration case study, taking as a target application a video compression kernel. The integrated toolset has been used to produce a Pareto front of evaluated system-level configurations.","PeriodicalId":130275,"journal":{"name":"2012 International Conference on Embedded Computer Systems (SAMOS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121215509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-16DOI: 10.1109/SAMOS.2012.6404198
A. Herkersdorf
Summary form only given. Cyber Physical Systems (CPS) design expands the horizon of traditional hardware/software systems engineering into the specifics of natural sciences such as physics or bio-chemistry. This is a new quality and inherent challenge of CPS since interdisciplinary skills, methods, tools and design flows, which originally werent even considered for mutual awareness, should now be linked, inter-work with each other and eventually be merged in order to achieve a holistic system co-optimization. At the same time, application domains in which CPS are playing increasingly important roles such as ecological electro-mobility, medical healthcare, ambient assisted living or all aspects around energy generation, distribution and control all can be characterized by vastly growing demands for compute performance. Multicore and manycore architectures, brought forward by all leading processor vendors, are the natural candidates for compute work (/race) horses within the cyber domain of CPS. However, the use of multicore processors in CPS requires levels of safety, security, real-time support and energy efficiency, which multicore processors for general purpose computing applications have typically not been designed for. In order to help reducing the complexity from the above described CPS inter-domain linkage challenges, this contribution to the Samos CPS special session discusses generic accelerators and hardware/software techniques that provide coverage for critical non-functional requirements of off-the-shelf multicore and MPSoC (Multi-Processor System on Chip) architectures. Our main focus is on suitable virtualization and self-organization techniques for CPS.
{"title":"Multicore enablement for Cyber Physical Systems","authors":"A. Herkersdorf","doi":"10.1109/SAMOS.2012.6404198","DOIUrl":"https://doi.org/10.1109/SAMOS.2012.6404198","url":null,"abstract":"Summary form only given. Cyber Physical Systems (CPS) design expands the horizon of traditional hardware/software systems engineering into the specifics of natural sciences such as physics or bio-chemistry. This is a new quality and inherent challenge of CPS since interdisciplinary skills, methods, tools and design flows, which originally werent even considered for mutual awareness, should now be linked, inter-work with each other and eventually be merged in order to achieve a holistic system co-optimization. At the same time, application domains in which CPS are playing increasingly important roles such as ecological electro-mobility, medical healthcare, ambient assisted living or all aspects around energy generation, distribution and control all can be characterized by vastly growing demands for compute performance. Multicore and manycore architectures, brought forward by all leading processor vendors, are the natural candidates for compute work (/race) horses within the cyber domain of CPS. However, the use of multicore processors in CPS requires levels of safety, security, real-time support and energy efficiency, which multicore processors for general purpose computing applications have typically not been designed for. In order to help reducing the complexity from the above described CPS inter-domain linkage challenges, this contribution to the Samos CPS special session discusses generic accelerators and hardware/software techniques that provide coverage for critical non-functional requirements of off-the-shelf multicore and MPSoC (Multi-Processor System on Chip) architectures. Our main focus is on suitable virtualization and self-organization techniques for CPS.","PeriodicalId":130275,"journal":{"name":"2012 International Conference on Embedded Computer Systems (SAMOS)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126834410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-16DOI: 10.1109/SAMOS.2012.6404190
D. May, W. Stechele
A recent approach to deal with the challenges that come along with the shrinking feature size of CMOS circuits is probabilistic computing. Those challenges, such as noise or process variations, result in a certain probabilistic behavior of the circuit and its gates. Probabilistic Computing, also referred to as pCMOS, does not try to avoid the occurrence of errors, but tries to determine the probability of errors at the output of the circuit, and to limit it to a value that the specific application can tolerate. Past research has shown that probabilistic computing has potential to drastically reduce the power consumption of circuits by scaling the supply voltage of gates to a value where they become non-deterministic, while tolerating a certain amount of probabilistic behavior at the output. Therefore, one main task in the design of pCMOS circuits is to determine the error probabilities at the output of the circuit, given a combination of error probabilities at the gates. In earlier work, pCMOS circuits have been characterized by memory-consuming and complex analytical calculations or by time-consuming software-based simulations. Hardware-accelerated emulators exist in large numbers, but miss the support of injecting errors with specified probabilities into as many circuit elements the user specifies at the same time. In this paper, we propose an FPGA-based fault simulator that allows for fast error probability classification, injection of errors at gate- and RT-level, and that is furthermore independent on the target architecture. Moreover, we demonstrate the usefulness of such a simulator by characterizing the probabilistic behavior of two benchmark circuits and reveal their energy-saving capability.
{"title":"An FPGA-based probability-aware fault simulator","authors":"D. May, W. Stechele","doi":"10.1109/SAMOS.2012.6404190","DOIUrl":"https://doi.org/10.1109/SAMOS.2012.6404190","url":null,"abstract":"A recent approach to deal with the challenges that come along with the shrinking feature size of CMOS circuits is probabilistic computing. Those challenges, such as noise or process variations, result in a certain probabilistic behavior of the circuit and its gates. Probabilistic Computing, also referred to as pCMOS, does not try to avoid the occurrence of errors, but tries to determine the probability of errors at the output of the circuit, and to limit it to a value that the specific application can tolerate. Past research has shown that probabilistic computing has potential to drastically reduce the power consumption of circuits by scaling the supply voltage of gates to a value where they become non-deterministic, while tolerating a certain amount of probabilistic behavior at the output. Therefore, one main task in the design of pCMOS circuits is to determine the error probabilities at the output of the circuit, given a combination of error probabilities at the gates. In earlier work, pCMOS circuits have been characterized by memory-consuming and complex analytical calculations or by time-consuming software-based simulations. Hardware-accelerated emulators exist in large numbers, but miss the support of injecting errors with specified probabilities into as many circuit elements the user specifies at the same time. In this paper, we propose an FPGA-based fault simulator that allows for fast error probability classification, injection of errors at gate- and RT-level, and that is furthermore independent on the target architecture. Moreover, we demonstrate the usefulness of such a simulator by characterizing the probabilistic behavior of two benchmark circuits and reveal their energy-saving capability.","PeriodicalId":130275,"journal":{"name":"2012 International Conference on Embedded Computer Systems (SAMOS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130126670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-16DOI: 10.1109/SAMOS.2012.6404196
Martin Schoeberl
Computer architects and researchers in the real-time domain start to investigate processors and architectures optimized for real-time systems. Optimized for real-time systems means time predictable, i.e., architectures where it is possible to statically derive a tight bound of the worst-case execution time. To compare different approaches we would like to quantify time predictability. That means we need to measure time predictability. In this paper we discuss the different approaches for these measurements and conclude that time predictability is practically not quantifiable. We can only compare the worst-case execution time bounds of different architectures.
{"title":"Is time predictability quantifiable?","authors":"Martin Schoeberl","doi":"10.1109/SAMOS.2012.6404196","DOIUrl":"https://doi.org/10.1109/SAMOS.2012.6404196","url":null,"abstract":"Computer architects and researchers in the real-time domain start to investigate processors and architectures optimized for real-time systems. Optimized for real-time systems means time predictable, i.e., architectures where it is possible to statically derive a tight bound of the worst-case execution time. To compare different approaches we would like to quantify time predictability. That means we need to measure time predictability. In this paper we discuss the different approaches for these measurements and conclude that time predictability is practically not quantifiable. We can only compare the worst-case execution time bounds of different architectures.","PeriodicalId":130275,"journal":{"name":"2012 International Conference on Embedded Computer Systems (SAMOS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117187024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：