I/O virtualization is utilized by cloud platforms to provide tenants with efficient, scalable, and manageable network and storage services. The de-facto industrial standard, paravirtualization, offers rich cloud functionality by introducing split front-end and back-end drivers in the guest and host operating systems, respectively. Given this fact, paravirtualization incurs host inefficiency and performance overhead. Thus, emerging hardware virtio accelerators (i.e., SRIOV-capable devices that conform to virtio specification) with device passthrough technologies mitigate the performance issue. However, adopting these devices presents the challenge of insufficient support for live migration. This paper proposes Un-IOV, a novel I/O virtualization system that simultaneously achieves bare-metal level I/O performance and migratability. The key idea is to develop a new hybrid virtualization stack with: (1) a host-bypassed direct data path for virtio accelerators, and (2) a relayed control path guaranteeing seamless live migration support. Un-IOV achieves high scalability by consuming minimum host resources. Extensive experiment results demonstrate that Un-IOV achieves superior network and storage virtualization performance than software implementations with comparable performance of direct passthrough I/O virtualization, while imposing zero guest modification (i.e., guest transparency).
{"title":"Un-IOV: Achieving Bare-Metal Level I/O Virtualization Performance for Cloud Usage With Migratability, Scalability and Transparency","authors":"Zongpu Zhang;Chenbo Xia;Cunming Liang;Jian Li;Chen Yu;Tiwei Bie;Roberts Martin;Daly Dan;Xiao Wang;Yong Liu;Haibing Guan","doi":"10.1109/TC.2024.3375589","DOIUrl":"10.1109/TC.2024.3375589","url":null,"abstract":"I/O virtualization is utilized by cloud platforms to provide tenants with efficient, scalable, and manageable network and storage services. The de-facto industrial standard, paravirtualization, offers rich cloud functionality by introducing split front-end and back-end drivers in the guest and host operating systems, respectively. Given this fact, paravirtualization incurs host inefficiency and performance overhead. Thus, emerging hardware virtio accelerators (i.e., SRIOV-capable devices that conform to virtio specification) with device passthrough technologies mitigate the performance issue. However, adopting these devices presents the challenge of insufficient support for live migration. This paper proposes Un-IOV, a novel I/O virtualization system that simultaneously achieves bare-metal level I/O performance and migratability. The key idea is to develop a new hybrid virtualization stack with: (1) a host-bypassed direct data path for virtio accelerators, and (2) a relayed control path guaranteeing seamless live migration support. Un-IOV achieves high scalability by consuming minimum host resources. Extensive experiment results demonstrate that Un-IOV achieves superior network and storage virtualization performance than software implementations with comparable performance of direct passthrough I/O virtualization, while imposing zero guest modification (i.e., guest transparency).","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"73 7","pages":"1655-1668"},"PeriodicalIF":3.7,"publicationDate":"2024-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140154872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Long timescale Molecular Dynamics (MD) simulation of small molecules is crucial in drug design and basic science. To accelerate a small data set that is executed for a large number of iterations, high-efficiency is required. Recent work in this domain has demonstrated that among COTS devices only FPGA-centric clusters can scale beyond a few processors. The problem addressed here is that, as the number of on-chip processors has increased from fewer than 10 into the hundreds, previous intra-chip routing solutions are no longer viable. We find, however, that through various design innovations, high efficiency can be maintained. These include replacing the previous broadcast networks with ring-routing and then augmenting the rings with out-of-order and caching mechanisms. Others are adding a level of hierarchical filtering and memory recycling. Two novel optimized architectures emerge, together with a number of variations. These are validated, analyzed, and evaluated. We find that in the domain of interest speed-ups over GPUs are achieved. The potential impact is that this system promises to be the basis for scalable long timescale MD with commodity clusters.
{"title":"FPGA-Accelerated Range-Limited Molecular Dynamics","authors":"Chunshu Wu;Chen Yang;Sahan Bandara;Tong Geng;Anqi Guo;Pouya Haghi;Ang Li;Martin Herbordt","doi":"10.1109/TC.2024.3375613","DOIUrl":"10.1109/TC.2024.3375613","url":null,"abstract":"Long timescale Molecular Dynamics (MD) simulation of small molecules is crucial in drug design and basic science. To accelerate a small data set that is executed for a large number of iterations, high-efficiency is required. Recent work in this domain has demonstrated that among COTS devices only FPGA-centric clusters can scale beyond a few processors. The problem addressed here is that, as the number of on-chip processors has increased from fewer than 10 into the hundreds, previous intra-chip routing solutions are no longer viable. We find, however, that through various design innovations, high efficiency can be maintained. These include replacing the previous broadcast networks with ring-routing and then augmenting the rings with out-of-order and caching mechanisms. Others are adding a level of hierarchical filtering and memory recycling. Two novel optimized architectures emerge, together with a number of variations. These are validated, analyzed, and evaluated. We find that in the domain of interest speed-ups over GPUs are achieved. The potential impact is that this system promises to be the basis for scalable long timescale MD with commodity clusters.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"73 6","pages":"1544-1558"},"PeriodicalIF":3.7,"publicationDate":"2024-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140154879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lulu Yao;Yongkun Li;Patrick P. C. Lee;Xiaoyang Wang;Yinlong Xu
Memory deduplication effectively relieves the memory space bottleneck by removing duplicate pages, especially in virtualized systems in which virtual machines run the same OS and similar applications. However, due to the non-uniform access latencies in NUMA architectures, memory deduplication poses a trade-off between memory savings and access performance: global deduplication across NUMA nodes realizes high memory savings, but leads to frequent cross-node remote access after deduplication and results in performance degradations. In contrast, local deduplication avoids remote access, but limits deduplication effectiveness. We design AdaptMD, an adaptive memory deduplication system that addresses the space-performance trade-off in NUMA architectures. AdaptMD leverages hotness awareness to globally deduplicate only cold pages to reduce remote access. It also migrates similar applications to the same NUMA node to allow local deduplication without remote access. We further make AdaptMD readily configurable to address various deployment scenarios. Experiments show that AdaptMD achieves high memory savings as in global deduplication, while achieving similar access performance as in local deduplication.
重复内存删除通过删除重复页面有效缓解了内存空间瓶颈，尤其是在虚拟机运行相同操作系统和类似应用程序的虚拟化系统中。然而，由于 NUMA 架构的访问延迟不均匀，重复数据删除需要在节省内存和访问性能之间做出权衡：跨 NUMA 节点的全局重复数据删除可节省大量内存，但会导致重复数据删除后频繁的跨节点远程访问，从而导致性能下降。相比之下，本地重复数据删除避免了远程访问，但却限制了重复数据删除的效果。我们设计的 AdaptMD 是一种自适应重复数据删除内存系统，可解决 NUMA 架构中空间与性能之间的权衡问题。AdaptMD 利用热度感知功能，只对冷页面进行全局重复数据删除，以减少远程访问。它还能将类似的应用程序迁移到相同的 NUMA 节点上，从而实现无需远程访问的本地重复数据删除。我们还进一步使 AdaptMD 易于配置，以应对各种部署场景。实验表明，AdaptMD 可以像全局重复数据删除一样节省大量内存，同时实现与本地重复数据删除类似的访问性能。
{"title":"AdaptMD: Balancing Space and Performance in NUMA Architectures With Adaptive Memory Deduplication","authors":"Lulu Yao;Yongkun Li;Patrick P. C. Lee;Xiaoyang Wang;Yinlong Xu","doi":"10.1109/TC.2024.3375592","DOIUrl":"10.1109/TC.2024.3375592","url":null,"abstract":"Memory deduplication effectively relieves the memory space bottleneck by removing duplicate pages, especially in virtualized systems in which virtual machines run the same OS and similar applications. However, due to the non-uniform access latencies in NUMA architectures, memory deduplication poses a trade-off between memory savings and access performance: global deduplication across NUMA nodes realizes high memory savings, but leads to frequent cross-node remote access after deduplication and results in performance degradations. In contrast, local deduplication avoids remote access, but limits deduplication effectiveness. We design AdaptMD, an adaptive memory deduplication system that addresses the space-performance trade-off in NUMA architectures. AdaptMD leverages hotness awareness to globally deduplicate only cold pages to reduce remote access. It also migrates similar applications to the same NUMA node to allow local deduplication without remote access. We further make AdaptMD readily configurable to address various deployment scenarios. Experiments show that AdaptMD achieves high memory savings as in global deduplication, while achieving similar access performance as in local deduplication.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"73 6","pages":"1588-1602"},"PeriodicalIF":3.7,"publicationDate":"2024-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140154876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we present a new method to find S-box circuits with optimal multiplicative complexity (MC), i.e., MC-optimal S-box circuits. We provide new observations for efficiently constructing circuits and computing MC, combined with a popular pathfinding algorithm named A*. In our search, the A* algorithm outputs a path of length MC, corresponding to an MC-optimal circuit. Based on an in-depth analysis of the process of computing MC, we enable the A* algorithm to function within our graph to investigate a wider range of S-boxes than existing methods such as the SAT-solver-based tool [1] and LIGHTER[2] . We provide implementable MC-optimal circuits for all the quadratic 5-bit bijective S-boxes and existing 5-bit almost-perfect nonlinear (APN) S-boxes. Furthermore, we present MC-optimal circuits for 6-bit S-boxes such as Sarkar Gold, Sarkar Quadratic, and some quadratic permutations. Finally, we theoretically demonstrate new lower bounds for the MCs of S-boxes, providing tighter bounds for the MCs of AES and MISTY S-boxes than previously known. This study complements previous results on MC-optimal S-box circuits and is intended to provide further insight into this field.
在本文中，我们提出了一种寻找具有最优乘法复杂度（MC）的 S-box 电路（即 MC-最优 S-box 电路）的新方法。我们为高效构建电路和计算 MC 提供了新的观测方法，并结合了一种名为 A* 的流行寻路算法。在我们的搜索中，A* 算法会输出一条长度为 MC 的路径，与 MC 最佳电路相对应。基于对 MC 计算过程的深入分析，与基于 SAT 求解器的工具 [1] 和 LIGHTER [2] 等现有方法相比，我们使 A* 算法在我们的图中能够研究更广泛的 S 框。我们为所有二次 5 位双射 S-box 和现有的 5 位几乎完全非线性 (APN) S-box 提供了可实现的 MC 最佳电路。此外，我们还提出了 6 位 S-box 的 MC 最佳电路，如 Sarkar Gold、Sarkar Quadratic 和一些二次排列。最后，我们从理论上证明了 S-box 的 MC 的新下限，为 AES 和 MISTY S-box 的 MC 提供了比以前已知的更严格的下限。这项研究补充了之前关于 MC 最佳 S-box 电路的结果，旨在为这一领域提供更深入的见解。
{"title":"Toward Finding S-Box Circuits With Optimal Multiplicative Complexity","authors":"Yongjin Jeon;Seungjun Baek;Jongsung Kim","doi":"10.1109/TC.2024.3398507","DOIUrl":"10.1109/TC.2024.3398507","url":null,"abstract":"In this paper, we present a new method to find S-box circuits with optimal multiplicative complexity (MC), i.e., MC-optimal S-box circuits. We provide new observations for efficiently constructing circuits and computing MC, combined with a popular pathfinding algorithm named A*. In our search, the A* algorithm outputs a path of length MC, corresponding to an MC-optimal circuit. Based on an in-depth analysis of the process of computing MC, we enable the A* algorithm to function within our graph to investigate a wider range of S-boxes than existing methods such as the SAT-solver-based tool \u0000<xref>[1]</xref>\u0000 and \u0000<monospace>LIGHTER</monospace>\u0000 \u0000<xref>[2]</xref>\u0000. We provide implementable MC-optimal circuits for all the quadratic 5-bit bijective S-boxes and existing 5-bit almost-perfect nonlinear (APN) S-boxes. Furthermore, we present MC-optimal circuits for 6-bit S-boxes such as Sarkar Gold, Sarkar Quadratic, and some quadratic permutations. Finally, we theoretically demonstrate new lower bounds for the MCs of S-boxes, providing tighter bounds for the MCs of \u0000<monospace>AES</monospace>\u0000 and \u0000<monospace>MISTY</monospace>\u0000 S-boxes than previously known. This study complements previous results on MC-optimal S-box circuits and is intended to provide further insight into this field.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"73 8","pages":"2036-2050"},"PeriodicalIF":3.6,"publicationDate":"2024-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140933829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As a primary component of Transformers, attention mechanism suffers from quadratic computational complexity. To achieve efficient implementations, its hardware accelerator designs have aroused great research interest. However, most existing accelerators only support a single type of application and a single type of attention, making it difficult to meet the demands of diverse application scenarios. Additionally, they mainly focus on the dynamic pruning of attention matrices, which requires the deployment of pre-processing units, thereby reducing overall hardware efficiency. This paper presents CoDA which is an algorithm, dataflow and architecture co-design framework for versatile and efficient attention accelerators. The designed accelerator supports both NLP and CV applications, and can be configured into the mode supporting low-rank attention or low-rank plus sparse attention. We apply algorithmic transformations to low-rank attention to significantly reduce computational complexity. To prevent an increase in storage overhead resulting from the proposed algorithmic transformations, we carefully design the dataflows and adopt a block-wise fashion. Down-scaling softmax is further supported by architecture and dataflow co-design. Moreover, we propose a softmax sharing strategy to reduce the area cost. Our experiment results demonstrate that the proposed accelerator outperforms the state-of-the-art designs in terms of throughput, area efficiency and energy efficiency.
{"title":"CoDA: A Co-Design Framework for Versatile and Efficient Attention Accelerators","authors":"Wenjie Li;Aokun Hu;Ningyi Xu;Guanghui He","doi":"10.1109/TC.2024.3398488","DOIUrl":"10.1109/TC.2024.3398488","url":null,"abstract":"As a primary component of Transformers, attention mechanism suffers from quadratic computational complexity. To achieve efficient implementations, its hardware accelerator designs have aroused great research interest. However, most existing accelerators only support a single type of application and a single type of attention, making it difficult to meet the demands of diverse application scenarios. Additionally, they mainly focus on the dynamic pruning of attention matrices, which requires the deployment of pre-processing units, thereby reducing overall hardware efficiency. This paper presents CoDA which is an algorithm, dataflow and architecture co-design framework for versatile and efficient attention accelerators. The designed accelerator supports both NLP and CV applications, and can be configured into the mode supporting low-rank attention or low-rank plus sparse attention. We apply algorithmic transformations to low-rank attention to significantly reduce computational complexity. To prevent an increase in storage overhead resulting from the proposed algorithmic transformations, we carefully design the dataflows and adopt a block-wise fashion. Down-scaling softmax is further supported by architecture and dataflow co-design. Moreover, we propose a softmax sharing strategy to reduce the area cost. Our experiment results demonstrate that the proposed accelerator outperforms the state-of-the-art designs in terms of throughput, area efficiency and energy efficiency.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"73 8","pages":"1924-1938"},"PeriodicalIF":3.6,"publicationDate":"2024-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140933994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiulong Liu;Zhiyuan Zheng;Wenbin Wang;Hao Xu;Fengjun Xiao;Keqiu Li
In Byzantine fault-tolerant (BFT) systems, maintaining consistency amidst malicious replicas is crucial, especially for blockchain systems. Recent innovations in this field have integrated multiple leaders into the BFT consensus mechanism to boost scalability and efficiency. However, the existing approaches often lead to excessive consumption of storage, bandwidth, and CPU resources due to redundant transactions. And the attempting to mitigate resource wastage inadvertently reduces resilience against Byzantine failures. To this end, we propose PeterHofe, an innovative ring-based approach for collaborative transaction processing. PeterHofe focuses on balancing resource utilization and minimizing the influence of Byzantine leaders, thereby enhancing transaction processing speed and overall system reliability. PeterHofe innovates by partitioning the transaction hash space into various buckets and creating a complex mappings between these buckets and the replicas, effectively reducing the control of Byzantine replicas. In developing PeterHofe, we concentrate on three primary objectives: 1) the creation of a permutation-based ring structure that enhances resistance to Byzantine censorship, backed by thorough mathematical proofs and analyses; 2) the development of a Prophecy-Implementation mechanism aimed at minimizing transaction replication while scrutinizing potential malicious activities; 3) to ensure the applicability of our proposed method across various types of multi-leader BFT consensus protocols, we have developed an additional asynchronous protocol to ensure consistent application of the packaging strategy. We have implemented PeterHofe using the latest significant frameworks, Narwhal and Tusk, and our empirical results affirm its capability to simultaneously minimize resource waste and bolster system robustness. Specifically, PeterHofe demonstrates efficiency in resource utilization, achieving a 20-fold reduction of resource waste when compared to the Random-based Strategy. When against the advanced Hash-based Partitioning Strategy, it reduces malicious transaction control by at least 66 $%$ , leading to up to 75 $%$ lower latency. In scenarios of high traffic, our approach significantly outperforms existing strategies in throughput. Against the Random-based Strategy, it achieves a 6.11 $%$ increase, and when compared to the Hash-based Partitioning Strategy, the improvement is 20 $%$ .
{"title":"Towards Cost-Effective and Robust Packaging in Multi-Leader BFT Blockchain Systems","authors":"Xiulong Liu;Zhiyuan Zheng;Wenbin Wang;Hao Xu;Fengjun Xiao;Keqiu Li","doi":"10.1109/TC.2024.3398510","DOIUrl":"10.1109/TC.2024.3398510","url":null,"abstract":"In Byzantine fault-tolerant (BFT) systems, maintaining consistency amidst malicious replicas is crucial, especially for blockchain systems. Recent innovations in this field have integrated multiple leaders into the BFT consensus mechanism to boost scalability and efficiency. However, the existing approaches often lead to excessive consumption of storage, bandwidth, and CPU resources due to redundant transactions. And the attempting to mitigate resource wastage inadvertently reduces resilience against Byzantine failures. To this end, we propose PeterHofe, an innovative ring-based approach for collaborative transaction processing. PeterHofe focuses on balancing resource utilization and minimizing the influence of Byzantine leaders, thereby enhancing transaction processing speed and overall system reliability. PeterHofe innovates by partitioning the transaction hash space into various buckets and creating a complex mappings between these buckets and the replicas, effectively reducing the control of Byzantine replicas. In developing PeterHofe, we concentrate on three primary objectives: 1) the creation of a permutation-based ring structure that enhances resistance to Byzantine censorship, backed by thorough mathematical proofs and analyses; 2) the development of a Prophecy-Implementation mechanism aimed at minimizing transaction replication while scrutinizing potential malicious activities; 3) to ensure the applicability of our proposed method across various types of multi-leader BFT consensus protocols, we have developed an additional asynchronous protocol to ensure consistent application of the packaging strategy. We have implemented PeterHofe using the latest significant frameworks, Narwhal and Tusk, and our empirical results affirm its capability to simultaneously minimize resource waste and bolster system robustness. Specifically, PeterHofe demonstrates efficiency in resource utilization, achieving a 20-fold reduction of resource waste when compared to the Random-based Strategy. When against the advanced Hash-based Partitioning Strategy, it reduces malicious transaction control by at least 66\u0000<inline-formula><tex-math>$%$</tex-math></inline-formula>\u0000, leading to up to 75\u0000<inline-formula><tex-math>$%$</tex-math></inline-formula>\u0000 lower latency. In scenarios of high traffic, our approach significantly outperforms existing strategies in throughput. Against the Random-based Strategy, it achieves a 6.11\u0000<inline-formula><tex-math>$%$</tex-math></inline-formula>\u0000 increase, and when compared to the Hash-based Partitioning Strategy, the improvement is 20\u0000<inline-formula><tex-math>$%$</tex-math></inline-formula>\u0000.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"73 11","pages":"2590-2604"},"PeriodicalIF":3.6,"publicationDate":"2024-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140933762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ensuring the reliability of deep neural networks (DNNs) is paramount in safety-critical applications. Although introducing supplementary fault-tolerant mechanisms can augment the reliability of DNNs, an efficiency tradeoff may be introduced. This study reveals the inherent fault tolerance of neural networks, where individual neurons exhibit varying degrees of fault tolerance, by thoroughly exploring the structural attributes of DNNs. We thereby develop a hardware/software collaborative method that guarantees the reliability of DNNs while minimizing performance degradation. We introduce the neuron vulnerability factor (NVF) to quantify the susceptibility to soft errors. We propose two efficient methods that leverage the NVF to minimize the negative effects of soft errors on neurons. First, we present a novel computational scheduling scheme. By prioritizing error-prone neurons, the expedited completion of their computations is facilitated to mitigate the risk of neural computing errors that arise from soft errors without sacrificing efficiency. Second, we propose the NVF-guided heterogeneous memory system. We employ variable-strength error-correcting codes and tailor their error-correction mechanisms to the vulnerability profile of specific neurons to ensure a highly targeted approach for error mitigation. Our experimental results demonstrate that the proposed scheme enhances the neural network accuracy by 18% on average, while significantly reducing the fault-tolerance overhead.
{"title":"Enhancing Neural Network Reliability: Insights From Hardware/Software Collaboration With Neuron Vulnerability Quantization","authors":"Jing Wang;Jinbin Zhu;Xin Fu;Di Zang;Keyao Li;Weigong Zhang","doi":"10.1109/TC.2024.3398492","DOIUrl":"10.1109/TC.2024.3398492","url":null,"abstract":"Ensuring the reliability of deep neural networks (DNNs) is paramount in safety-critical applications. Although introducing supplementary fault-tolerant mechanisms can augment the reliability of DNNs, an efficiency tradeoff may be introduced. This study reveals the inherent fault tolerance of neural networks, where individual neurons exhibit varying degrees of fault tolerance, by thoroughly exploring the structural attributes of DNNs. We thereby develop a hardware/software collaborative method that guarantees the reliability of DNNs while minimizing performance degradation. We introduce the neuron vulnerability factor (NVF) to quantify the susceptibility to soft errors. We propose two efficient methods that leverage the NVF to minimize the negative effects of soft errors on neurons. First, we present a novel computational scheduling scheme. By prioritizing error-prone neurons, the expedited completion of their computations is facilitated to mitigate the risk of neural computing errors that arise from soft errors without sacrificing efficiency. Second, we propose the NVF-guided heterogeneous memory system. We employ variable-strength error-correcting codes and tailor their error-correction mechanisms to the vulnerability profile of specific neurons to ensure a highly targeted approach for error mitigation. Our experimental results demonstrate that the proposed scheme enhances the neural network accuracy by 18% on average, while significantly reducing the fault-tolerance overhead.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"73 8","pages":"1953-1966"},"PeriodicalIF":3.6,"publicationDate":"2024-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140934198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we investigate the effects of violating the conditions of hash function uniformity and/or independence on the false positive probability of Bloom Filters (BF). To this end, we focus on hash functions of the H3 family with a partitioned memory organization for fast hardware implementations of BFs. We first introduce a dependence metric that quantifies hash function uniformity and independence. We then state and prove the necessary and sufficient conditions on the BF parameters for constructing uniform and independent hash functions. Finally, we derive an analytical expression for the exact false positive probability of a BF with hash functions that are not necessarily uniform or independent. We verify our expression with a hardware test bench and explore the effects of losing uniformity and independence through an experimental study that systematically sweeps different dependence metric values and numbers of hash functions. We demonstrate the effects of violating hash function uniformity and independence on the stated target false positive probability for selected previous works in the literature. As an important finding, we show that uniformity of individual hash functions is essential, whereas limited dependencies between hash functions can be tolerated without a negative effect on the false positive probability.
{"title":"Uniformity and Independence of H3 Hash Functions for Bloom Filters","authors":"Furkan Koltuk;Ece Güran Schmidt","doi":"10.1109/TC.2024.3398426","DOIUrl":"10.1109/TC.2024.3398426","url":null,"abstract":"In this paper, we investigate the effects of violating the conditions of hash function uniformity and/or independence on the false positive probability of Bloom Filters (BF). To this end, we focus on hash functions of the H3 family with a partitioned memory organization for fast hardware implementations of BFs. We first introduce a dependence metric that quantifies hash function uniformity and independence. We then state and prove the necessary and sufficient conditions on the BF parameters for constructing uniform and independent hash functions. Finally, we derive an analytical expression for the exact false positive probability of a BF with hash functions that are not necessarily uniform or independent. We verify our expression with a hardware test bench and explore the effects of losing uniformity and independence through an experimental study that systematically sweeps different dependence metric values and numbers of hash functions. We demonstrate the effects of violating hash function uniformity and independence on the stated target false positive probability for selected previous works in the literature. As an important finding, we show that uniformity of individual hash functions is essential, whereas limited dependencies between hash functions can be tolerated without a negative effect on the false positive probability.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"73 8","pages":"1913-1923"},"PeriodicalIF":3.6,"publicationDate":"2024-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140933826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, the flash-based Solid State Drive (SSD) array has been widely implemented in real-world large-scale clusters. With the increasing number of users in upper-tier applications and the burst of Input/Output requests in this data explosive era, data centers need to continuously scale up to meet real-time data storage needs. However, the classical disk array scaling methods are designed based on HDDs, ignoring the wear leveling and garbage collection characteristics of SSD. This leads to penalties due to the vast lifetime gap between extended SSDs and the original in-use SSDs while scaling the SSD array, including extra triggered wear leveling I/O, latency in average response time, etc. To address these problems, we propose an Adaptive Wear-Leveling aware data migration approach for flexible SSD array scaling in clusters. It manages the interdisk wear leveling based on Model Reference Adaptive Control, which includes an SSD behavior emulator, Kalman filter estimator, and adaptive law. To demonstrate the effectiveness of this approach, we conducted several simulations and implementations on actual hardware. The evaluation results show that Ada-WL has the self-adaptability to optimize the wear leveling management parameters for various states of SSD arrays, diverse workloads, and scaling performed multiple times, significantly improving performance for SSD array scaling.
{"title":"Ada-WL: An Adaptive Wear-Leveling Aware Data Migration Approach for Flexible SSD Array Scaling in Clusters","authors":"Yunfei Gu;Linhui Liu;Chentao Wu;Jie Li;Minyi Guo","doi":"10.1109/TC.2024.3398493","DOIUrl":"10.1109/TC.2024.3398493","url":null,"abstract":"Recently, the flash-based Solid State Drive (SSD) array has been widely implemented in real-world large-scale clusters. With the increasing number of users in upper-tier applications and the burst of Input/Output requests in this data explosive era, data centers need to continuously scale up to meet real-time data storage needs. However, the classical disk array scaling methods are designed based on HDDs, ignoring the wear leveling and garbage collection characteristics of SSD. This leads to penalties due to the vast lifetime gap between extended SSDs and the original in-use SSDs while scaling the SSD array, including extra triggered wear leveling I/O, latency in average response time, etc. To address these problems, we propose an Adaptive Wear-Leveling aware data migration approach for flexible SSD array scaling in clusters. It manages the interdisk wear leveling based on Model Reference Adaptive Control, which includes an SSD behavior emulator, Kalman filter estimator, and adaptive law. To demonstrate the effectiveness of this approach, we conducted several simulations and implementations on actual hardware. The evaluation results show that Ada-WL has the self-adaptability to optimize the wear leveling management parameters for various states of SSD arrays, diverse workloads, and scaling performed multiple times, significantly improving performance for SSD array scaling.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"73 8","pages":"1967-1982"},"PeriodicalIF":3.6,"publicationDate":"2024-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140933997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Unary computing is a relatively new method for implementing arbitrary nonlinear functions that uses unpacked thermometer number encoding, enabling much lower hardware costs. In its original form, unary computing provides no trade-off between accuracy and hardware cost. In this work, we propose a novel self-similarity-based method to optimize the previous hybrid binary-unary work and provide it with the trade-off between accuracy and hardware cost by introducing controlled levels of approximation. Looking for self-similarity between different parts of a function allows us to implement a very small subset of core unique subfunctions and derive the rest of the subfunctions from this core using simple linear transformations. We compare our method to previous works such as FloPoCo-LUT (lookup table), HBU (hybrid binary-unary) and FloPoCo-PPA (piecewise polynomial approximation) on several 8–12-bit nonlinear functions including Log, Exp, Sigmoid, GELU, Sin, and Sqr, which are frequently used in neural networks and image processing applications. The area $times$ delay hardware cost of our method is on average 32%–60% better than previous methods in both exact and approximate implementations. We also extend our method to multivariate nonlinear functions and show on average 78%–92% improvement over previous work.
{"title":"SimBU: Self-Similarity-Based Hybrid Binary-Unary Computing for Nonlinear Functions","authors":"Alireza Khataei;Gaurav Singh;Kia Bazargan","doi":"10.1109/TC.2024.3398512","DOIUrl":"10.1109/TC.2024.3398512","url":null,"abstract":"Unary computing is a relatively new method for implementing arbitrary nonlinear functions that uses unpacked thermometer number encoding, enabling much lower hardware costs. In its original form, unary computing provides no trade-off between accuracy and hardware cost. In this work, we propose a novel self-similarity-based method to optimize the previous hybrid binary-unary work and provide it with the trade-off between accuracy and hardware cost by introducing controlled levels of approximation. Looking for self-similarity between different parts of a function allows us to implement a very small subset of core unique subfunctions and derive the rest of the subfunctions from this core using simple linear transformations. We compare our method to previous works such as FloPoCo-LUT (lookup table), HBU (hybrid binary-unary) and FloPoCo-PPA (piecewise polynomial approximation) on several 8–12-bit nonlinear functions including Log, Exp, Sigmoid, GELU, Sin, and Sqr, which are frequently used in neural networks and image processing applications. The area \u0000<inline-formula><tex-math>$times$</tex-math></inline-formula>\u0000 delay hardware cost of our method is on average 32%–60% better than previous methods in both exact and approximate implementations. We also extend our method to multivariate nonlinear functions and show on average 78%–92% improvement over previous work.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"73 9","pages":"2192-2205"},"PeriodicalIF":3.6,"publicationDate":"2024-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140933756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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