Pub Date : 2008-09-23DOI: 10.1109/FPL.2008.4630039
Thilo Pionteck, C. Albrecht, R. Koch, E. Maehle
This paper explores the design space for runtime reconfigurable systems. A broad range of systems is surveyed and a set of parameters applicable for characterizing runtime reconfigurable systems is proposed. Compared to other surveys the focus is set on the system architecture, not on the underlying hardware structure. This allows a discussion that primarily considers the actual motivation for utilising runtime reconfiguration in system designs instead of discussing the limitations of actual hardware platforms.
{"title":"On the design parameters of runtime reconfigurable systems","authors":"Thilo Pionteck, C. Albrecht, R. Koch, E. Maehle","doi":"10.1109/FPL.2008.4630039","DOIUrl":"https://doi.org/10.1109/FPL.2008.4630039","url":null,"abstract":"This paper explores the design space for runtime reconfigurable systems. A broad range of systems is surveyed and a set of parameters applicable for characterizing runtime reconfigurable systems is proposed. Compared to other surveys the focus is set on the system architecture, not on the underlying hardware structure. This allows a discussion that primarily considers the actual motivation for utilising runtime reconfiguration in system designs instead of discussing the limitations of actual hardware platforms.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127375785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-23DOI: 10.1109/FPL.2008.4629947
J. Cuveland, F. Rettig, V. Angelov, V. Lindenstruth
An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high bandwidth (2.16 Tbit/s), low latency, and flexibility in the processing algorithm. The input data come optically via 1 080 links operating at 2.5 Gbit/s. The whole system is partitioned hierarchically in 18 groups of 5+1 modules and one top module. All modules contain the same PCB, FPGA, DDR SRAM and SDRAM, but are equipped with different optional components and additional interface boards, which simplifies the hardware development significantly and reduces the production costs. Embedded PowerPC processors running Linux systems are used to implement a control and monitoring system. The system was installed in the real environment in December 2007 and is in continuous operation for cosmic data taking.
{"title":"An FPGA-based high-speed, low-latency trigger processor for high-energy physics","authors":"J. Cuveland, F. Rettig, V. Angelov, V. Lindenstruth","doi":"10.1109/FPL.2008.4629947","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629947","url":null,"abstract":"An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high bandwidth (2.16 Tbit/s), low latency, and flexibility in the processing algorithm. The input data come optically via 1 080 links operating at 2.5 Gbit/s. The whole system is partitioned hierarchically in 18 groups of 5+1 modules and one top module. All modules contain the same PCB, FPGA, DDR SRAM and SDRAM, but are equipped with different optional components and additional interface boards, which simplifies the hardware development significantly and reduces the production costs. Embedded PowerPC processors running Linux systems are used to implement a control and monitoring system. The system was installed in the real environment in December 2007 and is in continuous operation for cosmic data taking.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125395683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-23DOI: 10.1109/FPL.2008.4629943
Daihan Wang, Hiroki Matsutani, H. Amano, M. Koibuchi
While the regular 2-D mesh topology has been utilized for most of network-on-chips (NoCs) on FPGAs, spatially biased traffic in some applications make some customization method feasible. A link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost with enough performance being kept. Two policies are proposed to avoid deadlocks and better performance can be achieved compared with up*/down* routing on the irregular topology with links removed. In the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation.
{"title":"A link removal methodology for Networks-on-Chip on reconfigurable systems","authors":"Daihan Wang, Hiroki Matsutani, H. Amano, M. Koibuchi","doi":"10.1109/FPL.2008.4629943","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629943","url":null,"abstract":"While the regular 2-D mesh topology has been utilized for most of network-on-chips (NoCs) on FPGAs, spatially biased traffic in some applications make some customization method feasible. A link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost with enough performance being kept. Two policies are proposed to avoid deadlocks and better performance can be achieved compared with up*/down* routing on the irregular topology with links removed. In the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122870306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-23DOI: 10.1109/FPL.2008.4630025
A. Guntoro, M. Glesner
In this paper, we present the design and the implementation of an FPGA-based floating-point adder with three inputs. The design is based on a 5-level pipeline stage in order to distribute the critical paths and to maximize the performance. We examine the data dependencies to minimize the number of the pipeline stages and to reduce the resource allocation. Our design is parameterisable in order to cope with different floating-point formats, including the standard IEEE 754 formats and the custom configurations. The proposed design with the single precision, 32-bit floating-point format, can be operated at 143 MHz on Xilinx Virtex2Pro XC2VP30-7.
{"title":"High-performance fpga-based floating-point adder with three inputs","authors":"A. Guntoro, M. Glesner","doi":"10.1109/FPL.2008.4630025","DOIUrl":"https://doi.org/10.1109/FPL.2008.4630025","url":null,"abstract":"In this paper, we present the design and the implementation of an FPGA-based floating-point adder with three inputs. The design is based on a 5-level pipeline stage in order to distribute the critical paths and to maximize the performance. We examine the data dependencies to minimize the number of the pipeline stages and to reduce the resource allocation. Our design is parameterisable in order to cope with different floating-point formats, including the standard IEEE 754 formats and the custom configurations. The proposed design with the single precision, 32-bit floating-point format, can be operated at 143 MHz on Xilinx Virtex2Pro XC2VP30-7.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129261476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-23DOI: 10.1109/FPL.2008.4629956
Josef Angermeier, Mateusz Majer, Jürgen Teich, L. Braun, T. Schwalb, P. Graf, M. Hubner, Jürgen Becker, Enno Lübbers, M. Platzner, C. Claus, W. Stechele, A. Herkersdorf, M. Rullmann, R. Merker
In this booth on fine grain reconfigurable architectures, several research groups demonstrate their joint work on operating concepts for managing dynamic and partial reconfiguration, visualization of bitstreams and routing, presenting an application applying dynamic reconfiguration for video engines as well as work on minimization of reconfiguration data. Unique is that all the above four projects present their work using the same reconfigurable FPGA-based fabric called Erlangen slot machine that has also been built within one project just the purpose of experimenting with dynamic fine grain reconfiguration as an interdisciplinary platform.
{"title":"SPP1148 booth: Fine grain reconfigurable architectures","authors":"Josef Angermeier, Mateusz Majer, Jürgen Teich, L. Braun, T. Schwalb, P. Graf, M. Hubner, Jürgen Becker, Enno Lübbers, M. Platzner, C. Claus, W. Stechele, A. Herkersdorf, M. Rullmann, R. Merker","doi":"10.1109/FPL.2008.4629956","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629956","url":null,"abstract":"In this booth on fine grain reconfigurable architectures, several research groups demonstrate their joint work on operating concepts for managing dynamic and partial reconfiguration, visualization of bitstreams and routing, presenting an application applying dynamic reconfiguration for video engines as well as work on minimization of reconfiguration data. Unique is that all the above four projects present their work using the same reconfigurable FPGA-based fabric called Erlangen slot machine that has also been built within one project just the purpose of experimenting with dynamic fine grain reconfiguration as an interdisciplinary platform.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124722569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-23DOI: 10.1109/FPL.2008.4629965
M. Silva, J. Ferreira
The paper presents a method for generating partial bitstreams on-line for use in systems with run-time reconfigurable FPGAs. Bitstream creation is performed at run-time by merging partial bitstreams from individual component modules. The process includes the capability to create connections between the modules by selection from a set of routes found during an off-line pre-processing step. Placement and interconnection of modules must follow a precise set of rules. While restricting the number of possible module arrangements, this approach allows bitstream creation to be performed with relatively few computational resources. Using a demonstration system with a Virtex-II Pro FPGA with a PowerPC 405 CPU, the process of creating at run-time a partial bitstream for 22% of the device area takes 24 ms.
本文提出了一种在线生成部分位流的方法，用于具有运行时可重构fpga的系统。比特流创建是在运行时通过合并来自各个组件模块的部分比特流来执行的。该过程包括通过从离线预处理步骤中找到的一组路由中进行选择，在模块之间创建连接的功能。模块的放置和连接必须遵循一套精确的规则。虽然限制了可能的模块排列数量，但这种方法允许用相对较少的计算资源来执行比特流创建。使用带有Virtex-II Pro FPGA和PowerPC 405 CPU的演示系统，在运行时创建占设备面积22%的部分比特流的过程需要24 ms。
{"title":"Generation of partial FPGA configurations at run-time","authors":"M. Silva, J. Ferreira","doi":"10.1109/FPL.2008.4629965","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629965","url":null,"abstract":"The paper presents a method for generating partial bitstreams on-line for use in systems with run-time reconfigurable FPGAs. Bitstream creation is performed at run-time by merging partial bitstreams from individual component modules. The process includes the capability to create connections between the modules by selection from a set of routes found during an off-line pre-processing step. Placement and interconnection of modules must follow a precise set of rules. While restricting the number of possible module arrangements, this approach allows bitstream creation to be performed with relatively few computational resources. Using a demonstration system with a Virtex-II Pro FPGA with a PowerPC 405 CPU, the process of creating at run-time a partial bitstream for 22% of the device area takes 24 ms.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123529963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-23DOI: 10.1109/FPL.2008.4630007
D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli, L. Torres
We consider multiprocessor system-on-chip (MP-SoC) integrating several processing elements (PE). These architectures require distributed and scalable control techniques for run-time optimization of applicative parameters. Our approach is to use the game theory as an optimization model to solve the trade-off issues at run-time. We applied it to the distributed dynamic voltage frequency scaling (DVFS) management, adjusting at run-time the frequency set of each PE based on the synchronization between tasks of the application graph and the PE temperature profile. Results show that the analyzed algorithm converges to a solution in about 94% of the cases and in less than 40 calculation cycles for a 100-processor MP-SoC. It reaches an average optimization of 89% compared to an off-line centralized reference but about 140 times faster when simulating.
{"title":"Convergence analysis of run-time distributed optimization on adaptive systems using game theory","authors":"D. Puschini, F. Clermidy, P. Benoit, G. Sassatelli, L. Torres","doi":"10.1109/FPL.2008.4630007","DOIUrl":"https://doi.org/10.1109/FPL.2008.4630007","url":null,"abstract":"We consider multiprocessor system-on-chip (MP-SoC) integrating several processing elements (PE). These architectures require distributed and scalable control techniques for run-time optimization of applicative parameters. Our approach is to use the game theory as an optimization model to solve the trade-off issues at run-time. We applied it to the distributed dynamic voltage frequency scaling (DVFS) management, adjusting at run-time the frequency set of each PE based on the synchronization between tasks of the application graph and the PE temperature profile. Results show that the analyzed algorithm converges to a solution in about 94% of the cases and in less than 40 calculation cycles for a 100-processor MP-SoC. It reaches an average optimization of 89% compared to an off-line centralized reference but about 140 times faster when simulating.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121293223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-23DOI: 10.1109/FPL.2008.4629919
J. Surís, C. Patterson, P. Athanas
It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents a dynamic router for Xilinx FPGAs, designed to run on stand-alone embedded systems. With information obtained from Xilinxpsilas XDL tool, a compact routing database for the Virtex-II/IIP/4 devices is built which only requires 96 KB of storage. A channel routing algorithm is used because of its deterministic execution time and because all routing resources in the channel are available. Sample channels are routed with the router and compared with the Xilinx PAR tool. Improvements in both execution time and in memory usage of several orders of magnitude are observed.
{"title":"An efficient run-time router for connecting modules in FPGAS","authors":"J. Surís, C. Patterson, P. Athanas","doi":"10.1109/FPL.2008.4629919","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629919","url":null,"abstract":"It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents a dynamic router for Xilinx FPGAs, designed to run on stand-alone embedded systems. With information obtained from Xilinxpsilas XDL tool, a compact routing database for the Virtex-II/IIP/4 devices is built which only requires 96 KB of storage. A channel routing algorithm is used because of its deterministic execution time and because all routing resources in the channel are available. Sample channels are routed with the router and compared with the Xilinx PAR tool. Improvements in both execution time and in memory usage of several orders of magnitude are observed.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116318202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-23DOI: 10.1109/FPL.2008.4630004
K. Tanigawa, Tetsuya Zuyama, Takuro Uchida, T. Hironaka
Aiming toward a compact high- throughput reconfigurable architecture, we propose the reconfigurable processor DS-HIE. In order to achieve the characteristics of compactness and high-throughput, the DS-HIE architecture executes operations following a bit-serial computation scheme and adopts a Benes network as its routing resource. Implementing bit-serial computation brings the advantage of small chip area and high throughput to the DS-HIE architecture, and the Benes network ensures the high availability of the routing paths within a compact chip area. In this paper, we explain several methods, namely two data transfer methods and three feedback path methods, and provide an evaluation of the architecture. The evaluation results showed that the structure which allows for the smallest chip area comprises the dedicated wiring method for data transfer and the area effort method for routing. Further, the transistor count of the DS-HIE processor is notably smaller than that of the core 2 duo processor.
{"title":"Exploring compact design on high throughput coarse grained reconfigurable architectures","authors":"K. Tanigawa, Tetsuya Zuyama, Takuro Uchida, T. Hironaka","doi":"10.1109/FPL.2008.4630004","DOIUrl":"https://doi.org/10.1109/FPL.2008.4630004","url":null,"abstract":"Aiming toward a compact high- throughput reconfigurable architecture, we propose the reconfigurable processor DS-HIE. In order to achieve the characteristics of compactness and high-throughput, the DS-HIE architecture executes operations following a bit-serial computation scheme and adopts a Benes network as its routing resource. Implementing bit-serial computation brings the advantage of small chip area and high throughput to the DS-HIE architecture, and the Benes network ensures the high availability of the routing paths within a compact chip area. In this paper, we explain several methods, namely two data transfer methods and three feedback path methods, and provide an evaluation of the architecture. The evaluation results showed that the structure which allows for the smallest chip area comprises the dedicated wiring method for data transfer and the area effort method for routing. Further, the transistor count of the DS-HIE processor is notably smaller than that of the core 2 duo processor.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126287700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-23DOI: 10.1109/FPL.2008.4629979
Eoin Creedon, M. Manzke
The direct connection of application logic to network logic allows parallel applications to better leverage the network resources. We present a hardware description language message passing application programming interface (HDL MP API) for FPGAs. This allows an application to operate both local and network resources in a uniform, scalable and portable manner, independent of the interconnect. We use the message passing communication paradigm with all necessary communication operations performed by dedicated control hardware, independently of the interconnect. Ethernet has been used as the interconnect to demonstrate the HDL MP API functionality for this proof of concept system. Parallel linear array matrix multiplication has been implemented and tested using the HDL MP API. This application demonstrates the scalability provided by the HDL MP API.
{"title":"Scalable high performance computing on FPGA clusters using message passing","authors":"Eoin Creedon, M. Manzke","doi":"10.1109/FPL.2008.4629979","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629979","url":null,"abstract":"The direct connection of application logic to network logic allows parallel applications to better leverage the network resources. We present a hardware description language message passing application programming interface (HDL MP API) for FPGAs. This allows an application to operate both local and network resources in a uniform, scalable and portable manner, independent of the interconnect. We use the message passing communication paradigm with all necessary communication operations performed by dedicated control hardware, independently of the interconnect. Ethernet has been used as the interconnect to demonstrate the HDL MP API functionality for this proof of concept system. Parallel linear array matrix multiplication has been implemented and tested using the HDL MP API. This application demonstrates the scalability provided by the HDL MP API.","PeriodicalId":137963,"journal":{"name":"2008 International Conference on Field Programmable Logic and Applications","volume":"30 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125699660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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