Pub Date : 1998-10-27DOI: 10.1109/RTCSA.1998.726415
Pao-Ann Hsiung, Farn Wang
The current technology of verification engineering requires well-trained personnel in logic and automata theory, who carefully tune their verification packages, to tame the well-known state-space explosion problem. Research has resulted in a large number of techniques for reducing the system state-space, such as symmetry-based reductions, partial-order semantics, bisimulation equivalences, etc. To let more people benefit from the technology of computer-aided verification even with little training in the related theories, a new tool called State-Graph Manipulator (SGM) was developed to package various sophisticated verification techniques as manipulators on state-graphs as high-level data-objects. An example user session of SGM is discussed and the results presented. Experiments conducted using SGM show how the tool, when used by a system designer can increase verification efficiency and scalability.
{"title":"A state graph manipulator tool for real-time system specification and verification","authors":"Pao-Ann Hsiung, Farn Wang","doi":"10.1109/RTCSA.1998.726415","DOIUrl":"https://doi.org/10.1109/RTCSA.1998.726415","url":null,"abstract":"The current technology of verification engineering requires well-trained personnel in logic and automata theory, who carefully tune their verification packages, to tame the well-known state-space explosion problem. Research has resulted in a large number of techniques for reducing the system state-space, such as symmetry-based reductions, partial-order semantics, bisimulation equivalences, etc. To let more people benefit from the technology of computer-aided verification even with little training in the related theories, a new tool called State-Graph Manipulator (SGM) was developed to package various sophisticated verification techniques as manipulators on state-graphs as high-level data-objects. An example user session of SGM is discussed and the results presented. Experiments conducted using SGM show how the tool, when used by a system designer can increase verification efficiency and scalability.","PeriodicalId":142319,"journal":{"name":"Proceedings Fifth International Conference on Real-Time Computing Systems and Applications (Cat. No.98EX236)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130670177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-27DOI: 10.1109/RTCSA.1998.726417
S. Nagano, T. Kikuno
We consider responsiveness verification of communication protocols on the client-server system CS/sub N/, which consists of one client site and N (N/spl ges/2) server sites, under the assumption that a single transient failure occurs on any one server site. For the verification, a typical naive method NAIV generates exhaustively all abnormal system states reachable after the failure, and then calculates the recovery time needed for returning to a normal state. We propose two simplified methods (RSY M and EST) to reduce the overheads needed for the method NAIV. The first method (RSY M) takes notice of symmetric properties on the system CS/sub N/ and considers the case where a single transient failure occurs on a specific server site. The second method (EST) verifies the responsiveness on the restricted system CS/sub 2/, and then estimates from its result the responsiveness on the system CS/sub N/. Then we perform simulation experiments to evaluate the proposed methods. The experimental results show that: the first method RSY M can reduce the overheads of the method NAIV, while keeping accuracy in evaluating the recovery time; and the second method EST succeeds in both reducing further the overheads of the method RSY M and assuring good approximation for the recovery time.
{"title":"Experimental evaluation of simplified verification methods for responsive communication protocols","authors":"S. Nagano, T. Kikuno","doi":"10.1109/RTCSA.1998.726417","DOIUrl":"https://doi.org/10.1109/RTCSA.1998.726417","url":null,"abstract":"We consider responsiveness verification of communication protocols on the client-server system CS/sub N/, which consists of one client site and N (N/spl ges/2) server sites, under the assumption that a single transient failure occurs on any one server site. For the verification, a typical naive method NAIV generates exhaustively all abnormal system states reachable after the failure, and then calculates the recovery time needed for returning to a normal state. We propose two simplified methods (RSY M and EST) to reduce the overheads needed for the method NAIV. The first method (RSY M) takes notice of symmetric properties on the system CS/sub N/ and considers the case where a single transient failure occurs on a specific server site. The second method (EST) verifies the responsiveness on the restricted system CS/sub 2/, and then estimates from its result the responsiveness on the system CS/sub N/. Then we perform simulation experiments to evaluate the proposed methods. The experimental results show that: the first method RSY M can reduce the overheads of the method NAIV, while keeping accuracy in evaluating the recovery time; and the second method EST succeeds in both reducing further the overheads of the method RSY M and assuring good approximation for the recovery time.","PeriodicalId":142319,"journal":{"name":"Proceedings Fifth International Conference on Real-Time Computing Systems and Applications (Cat. No.98EX236)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127936373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-27DOI: 10.1109/RTCSA.1998.726414
A. Nakata, T. Higashino, K. Taniguchi
We propose a protocol synthesis method based on a partial order model (called event structures) for the class of context-free processes. First, we assign a unique name called event ID to every event executable by a given service specification. An event ID is a finite sequence of symbols derived from the context-free process specification. Then we show that some interesting sets of events are expressible by regular expressions on symbols, and that the event structure can be finitely represented by a set of relations among the regular expressions. Finally, we present a method to derive a protocol specification which implements a given service specification on distributed nodes, by using the obtained finite representation of event structures. The derived protocol specification contains the minimum message exchanges necessary to ensure the partial order of events of the service specification.
{"title":"Protocol synthesis from context-free processes using event structures","authors":"A. Nakata, T. Higashino, K. Taniguchi","doi":"10.1109/RTCSA.1998.726414","DOIUrl":"https://doi.org/10.1109/RTCSA.1998.726414","url":null,"abstract":"We propose a protocol synthesis method based on a partial order model (called event structures) for the class of context-free processes. First, we assign a unique name called event ID to every event executable by a given service specification. An event ID is a finite sequence of symbols derived from the context-free process specification. Then we show that some interesting sets of events are expressible by regular expressions on symbols, and that the event structure can be finitely represented by a set of relations among the regular expressions. Finally, we present a method to derive a protocol specification which implements a given service specification on distributed nodes, by using the obtained finite representation of event structures. The derived protocol specification contains the minimum message exchanges necessary to ensure the partial order of events of the service specification.","PeriodicalId":142319,"journal":{"name":"Proceedings Fifth International Conference on Real-Time Computing Systems and Applications (Cat. No.98EX236)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134196125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-27DOI: 10.1109/RTCSA.1998.726412
Kristian Sandström, C. Eriksson, G. Fohler
The requirements of industrial applications only rarely permit the exclusive use of single paradigms in the development of real-time systems. Product cost, reuse of existing solutions, and efficiency require diverse, or even opposing methods to coexist or to be integrated. In this paper, we deal with one problem encountered during the development of a real-time system for motion control in automotive vehicles, the integration of static scheduling and interrupts. The user mandates pre run-time scheduling for a number of reasons, e.g., predictability, testability and low run-time overhead. However, the interrupt overhead cannot be ignored in a safety critical system, and therefore has to be accounted for when creating a static schedule. We propose a method that combines static scheduling and run-time interrupts by applying standard static scheduling techniques and exact analysis. The appropriateness of this method is underlined by successful industrial deployment.
{"title":"Handling interrupts with static scheduling in an automotive vehicle control system","authors":"Kristian Sandström, C. Eriksson, G. Fohler","doi":"10.1109/RTCSA.1998.726412","DOIUrl":"https://doi.org/10.1109/RTCSA.1998.726412","url":null,"abstract":"The requirements of industrial applications only rarely permit the exclusive use of single paradigms in the development of real-time systems. Product cost, reuse of existing solutions, and efficiency require diverse, or even opposing methods to coexist or to be integrated. In this paper, we deal with one problem encountered during the development of a real-time system for motion control in automotive vehicles, the integration of static scheduling and interrupts. The user mandates pre run-time scheduling for a number of reasons, e.g., predictability, testability and low run-time overhead. However, the interrupt overhead cannot be ignored in a safety critical system, and therefore has to be accounted for when creating a static schedule. We propose a method that combines static scheduling and run-time interrupts by applying standard static scheduling techniques and exact analysis. The appropriateness of this method is underlined by successful industrial deployment.","PeriodicalId":142319,"journal":{"name":"Proceedings Fifth International Conference on Real-Time Computing Systems and Applications (Cat. No.98EX236)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133332991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-27DOI: 10.1109/RTCSA.1998.726420
Toshihiko Kato, A. Kimura, Akira Hasegawa, Kenji Suzuki
Recently, it is required to transfer continuous media over networks without QoS guarantee. In these networks, network congestion will cause transmission delay variance which degrades the quality of continuous media itself. This paper proposes a new protocol using congestion control with two level rate control in the data transfer level and the coding level. It introduces a TCP-like congestion control mechanism to the rate control of the data transfer level, which can detect the QoS change quickly, and adjust the coding rate of continuous media with a time interval long enough for its quality. The performance evaluation through software simulation with multiplexing continuous media traffic and TCP traffic shows that the proposed protocol works effectively in the case of network congestion.
{"title":"Congestion control with two level rate control for continuous media traffic in network without QoS guarantee","authors":"Toshihiko Kato, A. Kimura, Akira Hasegawa, Kenji Suzuki","doi":"10.1109/RTCSA.1998.726420","DOIUrl":"https://doi.org/10.1109/RTCSA.1998.726420","url":null,"abstract":"Recently, it is required to transfer continuous media over networks without QoS guarantee. In these networks, network congestion will cause transmission delay variance which degrades the quality of continuous media itself. This paper proposes a new protocol using congestion control with two level rate control in the data transfer level and the coding level. It introduces a TCP-like congestion control mechanism to the rate control of the data transfer level, which can detect the QoS change quickly, and adjust the coding rate of continuous media with a time interval long enough for its quality. The performance evaluation through software simulation with multiplexing continuous media traffic and TCP traffic shows that the proposed protocol works effectively in the case of network congestion.","PeriodicalId":142319,"journal":{"name":"Proceedings Fifth International Conference on Real-Time Computing Systems and Applications (Cat. No.98EX236)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132704840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-27DOI: 10.1109/RTCSA.1998.726411
Sung-Soo Lim, Jihong Kim, S. Min
We propose a technique to analyze the worst case execution times (WCETs) of optimized programs. Our work is based on a hierarchical timing analysis technique called the extended timing schema (ETS). A major hurdle in applying the ETS to optimized programs is the lack of correspondences in the control structure between the optimized machine code to be analyzed and the original source program written in a high-level programming language. We suggest a compiler-assisted approach where a timing analyzer relies on an optimizing compiler for a consistent hierarchical representation and an accurate source-level correspondence that are essential for accurate WCET analysis for optimized programs. In order to validate the proposed approach, we implemented a proof-of-concept version of a timing analyzer for a 256-bit VLIW processor and compared the analysis results with the simulation results. The experimental results show that the proposed solution can accurately predict the WCETs of highly-optimized VLIW programs.
{"title":"A worst case timing analysis technique for optimized programs","authors":"Sung-Soo Lim, Jihong Kim, S. Min","doi":"10.1109/RTCSA.1998.726411","DOIUrl":"https://doi.org/10.1109/RTCSA.1998.726411","url":null,"abstract":"We propose a technique to analyze the worst case execution times (WCETs) of optimized programs. Our work is based on a hierarchical timing analysis technique called the extended timing schema (ETS). A major hurdle in applying the ETS to optimized programs is the lack of correspondences in the control structure between the optimized machine code to be analyzed and the original source program written in a high-level programming language. We suggest a compiler-assisted approach where a timing analyzer relies on an optimizing compiler for a consistent hierarchical representation and an accurate source-level correspondence that are essential for accurate WCET analysis for optimized programs. In order to validate the proposed approach, we implemented a proof-of-concept version of a timing analyzer for a 256-bit VLIW processor and compared the analysis results with the simulation results. The experimental results show that the proposed solution can accurately predict the WCETs of highly-optimized VLIW programs.","PeriodicalId":142319,"journal":{"name":"Proceedings Fifth International Conference on Real-Time Computing Systems and Applications (Cat. No.98EX236)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123923633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-27DOI: 10.1109/RTCSA.1998.726428
Chung-Leung Pang, C. Lam
In a distributed real-time database system (DRTDBS), transaction atomicity is ensured by commit protocol. If data conflict occurs between executing and committing transactions, system's performance will be affected. In this paper, based on the deadline driven conflict resolution (DDCR) approach proposed by Lam et al. (1997), we propose an enhancement called the DDCR with similarity (DDCR-S), to resolve the executing-committing conflicts in a DRTDBS with mixed requirements of criticality and consistency transactions. In the DDCR-S, conflicts involving transactions with looser consistency requirement, the notion of similarity is adopted so that a higher degree of concurrency can be achieved and at the same time the consistency requirements of the transactions can still be met. Simulation experiments have been performed and the results have shown that the use of DDCR-S can significantly improve the overall system performance.
{"title":"On using similarity for resolving conflicts at commit in mixed distributed real-time databases","authors":"Chung-Leung Pang, C. Lam","doi":"10.1109/RTCSA.1998.726428","DOIUrl":"https://doi.org/10.1109/RTCSA.1998.726428","url":null,"abstract":"In a distributed real-time database system (DRTDBS), transaction atomicity is ensured by commit protocol. If data conflict occurs between executing and committing transactions, system's performance will be affected. In this paper, based on the deadline driven conflict resolution (DDCR) approach proposed by Lam et al. (1997), we propose an enhancement called the DDCR with similarity (DDCR-S), to resolve the executing-committing conflicts in a DRTDBS with mixed requirements of criticality and consistency transactions. In the DDCR-S, conflicts involving transactions with looser consistency requirement, the notion of similarity is adopted so that a higher degree of concurrency can be achieved and at the same time the consistency requirements of the transactions can still be met. Simulation experiments have been performed and the results have shown that the use of DDCR-S can significantly improve the overall system performance.","PeriodicalId":142319,"journal":{"name":"Proceedings Fifth International Conference on Real-Time Computing Systems and Applications (Cat. No.98EX236)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129730517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-27DOI: 10.1109/RTCSA.1998.726409
Chunhee Lee, Won Ryu, Kihyun Song, Kyunghee Choi, Gihyun Jung, Seungkyu Park
The paper proposes online scheduling algorithms that reduce the largest weighted error incurred by preemptive imprecise tasks running on a single processor system. The first one is a two level algorithm. The top level scheduling, which is executed whenever a new task arrives, determines the processing times to be allotted to tasks in such a way to minimize maximum weighted error as well as to minimize total error. The lower level algorithm actually allocates the processor to the tasks. The second algorithm extends the online algorithm studied by W.K. Shih and J.W.S. Liu (1992) by formalizing the top level algorithm mathematically. The numerical simulation shows that the proposed algorithm outperforms the previous works in the sense that it greatly reduces the largest weighted error.
{"title":"On-line scheduling algorithms for reducing the largest weighted error incurred by imprecise tasks","authors":"Chunhee Lee, Won Ryu, Kihyun Song, Kyunghee Choi, Gihyun Jung, Seungkyu Park","doi":"10.1109/RTCSA.1998.726409","DOIUrl":"https://doi.org/10.1109/RTCSA.1998.726409","url":null,"abstract":"The paper proposes online scheduling algorithms that reduce the largest weighted error incurred by preemptive imprecise tasks running on a single processor system. The first one is a two level algorithm. The top level scheduling, which is executed whenever a new task arrives, determines the processing times to be allotted to tasks in such a way to minimize maximum weighted error as well as to minimize total error. The lower level algorithm actually allocates the processor to the tasks. The second algorithm extends the online algorithm studied by W.K. Shih and J.W.S. Liu (1992) by formalizing the top level algorithm mathematically. The numerical simulation shows that the proposed algorithm outperforms the previous works in the sense that it greatly reduces the largest weighted error.","PeriodicalId":142319,"journal":{"name":"Proceedings Fifth International Conference on Real-Time Computing Systems and Applications (Cat. No.98EX236)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126865663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-27DOI: 10.1109/RTCSA.1998.726422
M. Caccamo, G. Buttazzo
Time redundancy is an effective method for achieving fault tolerance in a real time system, when space redundancy cannot be used for cost or weight constraints. The paper presents a fault tolerant scheduling algorithm for real time systems consisting of firm and hard periodic tasks. Firm tasks can occasionally skip one instance according to a predefined quality of service parameter, whereas hard tasks include a primary and a backup job. The proposed scheduling algorithm ensures that each task instance is satisfied within its timing constraints by either the primary or the backup job. Moreover the algorithm maximizes the processor idle time available for processing primary jobs and automatically reclaims the spare time saved by deallocating backup jobs. A very interesting feature of the algorithm is that it can be tuned to balance performance versus complexity, so easily conforming to application's requirements.
{"title":"Optimal scheduling for fault-tolerant and firm real-time systems","authors":"M. Caccamo, G. Buttazzo","doi":"10.1109/RTCSA.1998.726422","DOIUrl":"https://doi.org/10.1109/RTCSA.1998.726422","url":null,"abstract":"Time redundancy is an effective method for achieving fault tolerance in a real time system, when space redundancy cannot be used for cost or weight constraints. The paper presents a fault tolerant scheduling algorithm for real time systems consisting of firm and hard periodic tasks. Firm tasks can occasionally skip one instance according to a predefined quality of service parameter, whereas hard tasks include a primary and a backup job. The proposed scheduling algorithm ensures that each task instance is satisfied within its timing constraints by either the primary or the backup job. Moreover the algorithm maximizes the processor idle time available for processing primary jobs and automatically reclaims the spare time saved by deallocating backup jobs. A very interesting feature of the algorithm is that it can be tuned to balance performance versus complexity, so easily conforming to application's requirements.","PeriodicalId":142319,"journal":{"name":"Proceedings Fifth International Conference on Real-Time Computing Systems and Applications (Cat. No.98EX236)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122254557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-27DOI: 10.1109/RTCSA.1998.726425
A. Casile, G. Buttazzo, Gerardo Lamastra, G. Lipari
This paper describes a tool for the design, simulation and analysis of real-time systems, ranging from simple scenarios with a few types of tasks on a single node to very complex architectures consisting of multiple nodes interconnected with a network and sharing a set of hardware and software resources. The tool is based on a discrete event simulation library, a scripting language describing the system load and the relevant measures, and a graphical interface providing user-friendly interaction with the simulator.
{"title":"Simulation and tracing of hybrid task sets on distributed systems","authors":"A. Casile, G. Buttazzo, Gerardo Lamastra, G. Lipari","doi":"10.1109/RTCSA.1998.726425","DOIUrl":"https://doi.org/10.1109/RTCSA.1998.726425","url":null,"abstract":"This paper describes a tool for the design, simulation and analysis of real-time systems, ranging from simple scenarios with a few types of tasks on a single node to very complex architectures consisting of multiple nodes interconnected with a network and sharing a set of hardware and software resources. The tool is based on a discrete event simulation library, a scripting language describing the system load and the relevant measures, and a graphical interface providing user-friendly interaction with the simulator.","PeriodicalId":142319,"journal":{"name":"Proceedings Fifth International Conference on Real-Time Computing Systems and Applications (Cat. No.98EX236)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121599887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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