Current-mode Analog-to-Digital Converter (ADC) has drawn many attentions due to its high operating speed, power and ground noise immunity, and etc. However, 2n -- 1 comparators are required in traditional n-bit current-mode ADC design, leading to inevitable high power consumption and large chip area. In this work, we propose a low power and compact current mode Multi-Threshold Comparator (MTC) based on giant Spin Hall Effect (SHE). The two threshold currents of the proposed SHE-MTC are 200μA and 250μA with 1ns switching time, respectively. The proposed current-mode hybrid spin-CMOS flash ADC based on SHE-MTC reduces the number of comparators almost by half (2n-1), thus correspondingly reducing the required current mirror branches, total power consumption and chip area. Moreover, due to the non-volatility of SHE-MTC, the front-end analog circuits can be switched off when it is not required to further increase power efficiency. The device dynamics of SHE-MTC is simulated using a numerical device model based on Landau-Lifshitz-Gilbert (LLG) equation with Spin-Transfer Torque (STT) term and SHE term. The device-circuit co-simulation in SPICE (45nm CMOS technology) have shown that the average power dissipation of proposed ADC is 1.9mW, operating at 500MS/s with 1.2 V power supply. The INL and DNL are in the range of 0.23LSB and 0.32LSB, respectively.
{"title":"A Low Power Current-Mode Flash ADC with Spin Hall Effect based Multi-Threshold Comparator","authors":"Zhezhi He, Deliang Fan","doi":"10.1145/2934583.2934642","DOIUrl":"https://doi.org/10.1145/2934583.2934642","url":null,"abstract":"Current-mode Analog-to-Digital Converter (ADC) has drawn many attentions due to its high operating speed, power and ground noise immunity, and etc. However, 2n -- 1 comparators are required in traditional n-bit current-mode ADC design, leading to inevitable high power consumption and large chip area. In this work, we propose a low power and compact current mode Multi-Threshold Comparator (MTC) based on giant Spin Hall Effect (SHE). The two threshold currents of the proposed SHE-MTC are 200μA and 250μA with 1ns switching time, respectively. The proposed current-mode hybrid spin-CMOS flash ADC based on SHE-MTC reduces the number of comparators almost by half (2n-1), thus correspondingly reducing the required current mirror branches, total power consumption and chip area. Moreover, due to the non-volatility of SHE-MTC, the front-end analog circuits can be switched off when it is not required to further increase power efficiency. The device dynamics of SHE-MTC is simulated using a numerical device model based on Landau-Lifshitz-Gilbert (LLG) equation with Spin-Transfer Torque (STT) term and SHE term. The device-circuit co-simulation in SPICE (45nm CMOS technology) have shown that the average power dissipation of proposed ADC is 1.9mW, operating at 500MS/s with 1.2 V power supply. The INL and DNL are in the range of 0.23LSB and 0.32LSB, respectively.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117250573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P1801 is an IEEE-SA entity based work-group that consists of a wide range of participants including EDA, Semiconductor companies and IP-providers. 1801-2015 is the latest revision of the standard that made it,s first debut in 2009. This talk will give an overview of IEEE 1801-2015, and elaborate on the new capabilities and updates in 2015 compared to the previous standard release. Some of the key updates that will be discussed include: • A major revision of the definition of power states and transitions. • New concepts related to hard and soft macros and bottom-up implementation. • Support for IP component power modeling for system level power analysis. • Generalization of supply states to apply to all supply objects, not just ports. • Generalization of power models to represent hard and soft macros, power models, etc. • New Power groups concept for defining a group of related power states. • Support for user-defined supply resolution functions and related semantics. • Support for find_objects to find supply ports. • Ability to map repeater strategies to library cells. • New model for nominal supply values, supply source variation, and correlation. • Clarification of level shifting insertion algorithm, and removal of default level shifter strategy. • New Information Model (clause 10) and API (UPF packages and Tcl bindings). • New Query functions. • New usage examples illustrating Successive Refinement and Bottom-Up implementation.
{"title":"Overview of IEEE1801-2015: Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems: Invited Paper","authors":"Sushma Honnavara-Prasad","doi":"10.1145/2934583.2962724","DOIUrl":"https://doi.org/10.1145/2934583.2962724","url":null,"abstract":"P1801 is an IEEE-SA entity based work-group that consists of a wide range of participants including EDA, Semiconductor companies and IP-providers. 1801-2015 is the latest revision of the standard that made it,s first debut in 2009. This talk will give an overview of IEEE 1801-2015, and elaborate on the new capabilities and updates in 2015 compared to the previous standard release. Some of the key updates that will be discussed include: • A major revision of the definition of power states and transitions. • New concepts related to hard and soft macros and bottom-up implementation. • Support for IP component power modeling for system level power analysis. • Generalization of supply states to apply to all supply objects, not just ports. • Generalization of power models to represent hard and soft macros, power models, etc. • New Power groups concept for defining a group of related power states. • Support for user-defined supply resolution functions and related semantics. • Support for find_objects to find supply ports. • Ability to map repeater strategies to library cells. • New model for nominal supply values, supply source variation, and correlation. • Clarification of level shifting insertion algorithm, and removal of default level shifter strategy. • New Information Model (clause 10) and API (UPF packages and Tcl bindings). • New Query functions. • New usage examples illustrating Successive Refinement and Bottom-Up implementation.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125409741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent ten years, lots of new applications emerged, such as AI, big data and cloud. Though the workloads of these applications are very diverse, they demand huge resource of data center. In contrast, the silicon technology moves slower and slower because the Moore's law is going to the end. Consequently, the data center building from commodity hardware cannot provide enough cost-efficiency and power-efficiency. To meet the increasingly resource needs of emerging applications, the scale of data center is become much larger and larger. It consumes huge power and cost of hardware. From the business perspective, the slow development of hardware technology limits the value creation of emerging applications. We, Baidu, the largest search engine in China, have faced this challenge in several years ago. We find that the server number increases much faster than the scale of business. And this case is common for internet companies. Because the iteration of general processor becomes slower and slower. For example, Intel announced that the Tick-Tock production strategic was out of date in this early year. This problem drive us to look for new methods to boost business. From Internet Company's perspective, building new chips or new architecture based on its applications' characteristics makes sense. This method can break the limitation of commodity chips and commodity hardware. And according to academic and industry experiences, domain-specified architecture can achieve much better performance and power efficiency than general architecture. Consequently, we are exploring new architecture to extend Moore's law. In this paper, we present the works on exploring new architecture for data center. The data center resource includes storage, memory, computing and networking. Hence, we focus on these four areas. Firstly, we implemented SDF for large-scale distributed storage system. The SDF aims to low cost and high performance flash storage system. Secondly, we implemented SDA for deep learning big data. The SDA is dedicated to solve the computing bottle of emerging applications. The left paper is organized as following. The section 2 is about SDF [1]. The section 3 describes SDA for deep learning [2]. Section 4 presents SDA for big data [3]. And the last section is the conclusion.
{"title":"Extending the Moore's law by exploring new data center architecture: Invited Paper","authors":"Jian Ouyang, Wei Qi, Yong Wang","doi":"10.1145/2934583.2953981","DOIUrl":"https://doi.org/10.1145/2934583.2953981","url":null,"abstract":"In recent ten years, lots of new applications emerged, such as AI, big data and cloud. Though the workloads of these applications are very diverse, they demand huge resource of data center. In contrast, the silicon technology moves slower and slower because the Moore's law is going to the end. Consequently, the data center building from commodity hardware cannot provide enough cost-efficiency and power-efficiency. To meet the increasingly resource needs of emerging applications, the scale of data center is become much larger and larger. It consumes huge power and cost of hardware. From the business perspective, the slow development of hardware technology limits the value creation of emerging applications. We, Baidu, the largest search engine in China, have faced this challenge in several years ago. We find that the server number increases much faster than the scale of business. And this case is common for internet companies. Because the iteration of general processor becomes slower and slower. For example, Intel announced that the Tick-Tock production strategic was out of date in this early year. This problem drive us to look for new methods to boost business. From Internet Company's perspective, building new chips or new architecture based on its applications' characteristics makes sense. This method can break the limitation of commodity chips and commodity hardware. And according to academic and industry experiences, domain-specified architecture can achieve much better performance and power efficiency than general architecture. Consequently, we are exploring new architecture to extend Moore's law. In this paper, we present the works on exploring new architecture for data center. The data center resource includes storage, memory, computing and networking. Hence, we focus on these four areas. Firstly, we implemented SDF for large-scale distributed storage system. The SDF aims to low cost and high performance flash storage system. Secondly, we implemented SDA for deep learning big data. The SDA is dedicated to solve the computing bottle of emerging applications. The left paper is organized as following. The section 2 is about SDF [1]. The section 3 describes SDA for deep learning [2]. Section 4 presents SDA for big data [3]. And the last section is the conclusion.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"1650 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122705067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modern many-core systems must cope with a wide range of heterogeneity due to both manufacturing process variations and extreme requirements of multi-application, multithreaded workloads. The latter is increasingly challenging in the context of different performance constraints per multithreaded application. Existing thread mapping methods primarily focus on maximizing performance under a global power budget, failing to provide thread- and application-specific performance guarantees. This paper provides a comprehensive approach for variation- and workload-aware thread mapping on heterogeneous multi-core systems that satisfies per-application performance requirements and is manufacturing process variation-aware, while providing an analysis of its robustness to uncertainties in the power and performance models. We formulate the variation-aware mapping problem as a constrained 0-1 integer linear program (ILP) and we propose a heuristic-based algorithm for efficiently solving it. Compared with an optimal solver, our method produces results less than 10% away from optimum on average, with four orders of magnitude improvement in runtime. Moreover, the newly proposed method is robust to model uncertainty and in meeting per application performance requirements, while agnostic approaches result in performance bound violations (up to 100% in many cases).
{"title":"Can We Guarantee Performance Requirements under Workload and Process Variations?","authors":"Dimitrios Stamoulis, Diana Marculescu","doi":"10.1145/2934583.2934641","DOIUrl":"https://doi.org/10.1145/2934583.2934641","url":null,"abstract":"Modern many-core systems must cope with a wide range of heterogeneity due to both manufacturing process variations and extreme requirements of multi-application, multithreaded workloads. The latter is increasingly challenging in the context of different performance constraints per multithreaded application. Existing thread mapping methods primarily focus on maximizing performance under a global power budget, failing to provide thread- and application-specific performance guarantees. This paper provides a comprehensive approach for variation- and workload-aware thread mapping on heterogeneous multi-core systems that satisfies per-application performance requirements and is manufacturing process variation-aware, while providing an analysis of its robustness to uncertainties in the power and performance models. We formulate the variation-aware mapping problem as a constrained 0-1 integer linear program (ILP) and we propose a heuristic-based algorithm for efficiently solving it. Compared with an optimal solver, our method produces results less than 10% away from optimum on average, with four orders of magnitude improvement in runtime. Moreover, the newly proposed method is robust to model uncertainty and in meeting per application performance requirements, while agnostic approaches result in performance bound violations (up to 100% in many cases).","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128702230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Rachala, Miguel Rodriguez, S. Kosonocky, Milos Trajkovic
This paper describes modeling and implementation of a fully digital integrated linear voltage regulation system implemented in a 28nm x86-64 core to reduce power gating entry or exit latency. Running on a 100 MHz clock, the controller samples voltage using a time-to-digital converter, and controls a set of PFETs organized in a ring topology around the CPU cores to drop voltage down to a specified target value. A simple analytical model is developed and validated through fast Matlab-Simulink simulation, enabling quick design turnaround and reducing schedule impact. The regulation system is designed to support input-output voltages in the range 1.3 V - 0.55 V. Digitally-controlled header resistance values range from 1.5 Ω to 2 mΩ. Stable processor behavior is observed down to 0.6 V, enabling fast pseudo-power gating entry and exit. In a high-performance x86-64 dual-core microprocessor chip, the controller enables an effective 6% frequency increase for lightly threaded applications by increasing the boost state residency.
本文描述了在28nm x86-64内核中实现的全数字集成线性电压调节系统的建模和实现，以减少功率门控进入或退出延迟。在100mhz时钟上运行，控制器使用时间-数字转换器对电压进行采样，并控制一组围绕CPU内核以环形拓扑结构组织的pfet，以将电压降至指定的目标值。通过快速Matlab-Simulink仿真，开发并验证了一个简单的分析模型，从而实现快速设计周转并减少进度影响。调节系统的设计支持输入输出电压范围在1.3 V - 0.55 V。数字控制头电阻值范围从1.5 Ω到2 mΩ。稳定的处理器行为被观察到低至0.6 V，使快速伪功率门控进入和退出。在高性能x86-64双核微处理器芯片中，该控制器通过增加升压状态驻留，使轻线程应用的频率有效提高6%。
{"title":"Modeling and implementation of a fully-digital integrated per-core voltage regulation system in a 28nm high performance 64-bit processor","authors":"R. Rachala, Miguel Rodriguez, S. Kosonocky, Milos Trajkovic","doi":"10.1145/2934583.2934586","DOIUrl":"https://doi.org/10.1145/2934583.2934586","url":null,"abstract":"This paper describes modeling and implementation of a fully digital integrated linear voltage regulation system implemented in a 28nm x86-64 core to reduce power gating entry or exit latency. Running on a 100 MHz clock, the controller samples voltage using a time-to-digital converter, and controls a set of PFETs organized in a ring topology around the CPU cores to drop voltage down to a specified target value. A simple analytical model is developed and validated through fast Matlab-Simulink simulation, enabling quick design turnaround and reducing schedule impact. The regulation system is designed to support input-output voltages in the range 1.3 V - 0.55 V. Digitally-controlled header resistance values range from 1.5 Ω to 2 mΩ. Stable processor behavior is observed down to 0.6 V, enabling fast pseudo-power gating entry and exit. In a high-performance x86-64 dual-core microprocessor chip, the controller enables an effective 6% frequency increase for lightly threaded applications by increasing the boost state residency.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129475561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Session details: Non-Volatile Memory: Technology & System","authors":"Yongpan Liu, S. Mukhopadhyay","doi":"10.1145/3256023","DOIUrl":"https://doi.org/10.1145/3256023","url":null,"abstract":"","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124342661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kwang Min Kim, S. Sinha, B. Cline, G. Yeric, S. Lim
Monolithic 3D IC is an emerging technology to continuously satisfy demands for power reduction under challenges posed by traditional device scaling. In this paper, for the first time, we study power benefits of 4-tier monolithic 3D ICs compared with 2-tier monolithic 3D and 2D ICs. We present a tier partitioning methodology that significantly extends the capability of a state-of-the-art flow built for 2-tier monolithic 3D ICs. We develop two complete RTL-to-GDSII design flows to achieve this goal and offer quantitative comparisons. In addition, we study impacts of inter-tier via usage on 2-tier and 4-tier monolithic 3D ICs. Our experiments show that poorly controlled inter-tier via usage results in up to 6.05% degradation in total power savings. Thus, we develop an effective strategy to achieve inter-tier via configurations to optimize power metrics. Experiments show that 4-tier monolithic 3D ICs outperform 2-tier and 2D IC by 15% and 50% in terms of power and 25% and 75% in area under the same performance.
{"title":"Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study","authors":"Kwang Min Kim, S. Sinha, B. Cline, G. Yeric, S. Lim","doi":"10.1145/2934583.2934623","DOIUrl":"https://doi.org/10.1145/2934583.2934623","url":null,"abstract":"Monolithic 3D IC is an emerging technology to continuously satisfy demands for power reduction under challenges posed by traditional device scaling. In this paper, for the first time, we study power benefits of 4-tier monolithic 3D ICs compared with 2-tier monolithic 3D and 2D ICs. We present a tier partitioning methodology that significantly extends the capability of a state-of-the-art flow built for 2-tier monolithic 3D ICs. We develop two complete RTL-to-GDSII design flows to achieve this goal and offer quantitative comparisons. In addition, we study impacts of inter-tier via usage on 2-tier and 4-tier monolithic 3D ICs. Our experiments show that poorly controlled inter-tier via usage results in up to 6.05% degradation in total power savings. Thus, we develop an effective strategy to achieve inter-tier via configurations to optimize power metrics. Experiments show that 4-tier monolithic 3D ICs outperform 2-tier and 2D IC by 15% and 50% in terms of power and 25% and 75% in area under the same performance.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133869351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dynamic Voltage and Frequency Scaling (DVFS) is a widely used methodology to reduce the power consumption of mobile devices. This scheme performs frequency scaling in accordance with a specific governor and sets an operating voltage to be paired with the frequency. Temperature is one of the critical parameters affecting device operation. Practically, a guard-band exists in the operating voltage to ensure safe processor operation even at the worst temperature. DVFS can be optimized in terms of operating voltage under nominal conditions. In this paper, we propose a Temperature-aware DVS (T-DVS) that aggressively reduces the voltage guard-band. We explore the opportunity of providing the minimum operating voltages for frequencies at different temperatures and realize a dynamic voltage control scheme to optimize power consumption. The effectiveness of T-DVS is validated under various thermal conditions by using multi-core application processor. We experimentally observe that T-DVS leads to voltage gain without performance degradation regardless of both thermal conditions and chip characteristics. We show by using off-the-shelf smartphones that the voltage gain achieved by the scheme results in battery lifetime increment.
{"title":"T-DVS: Temperature-aware DVS based on Temperature Inversion Phenomenon","authors":"Jinsoo Park, H. Cha","doi":"10.1145/2934583.2934631","DOIUrl":"https://doi.org/10.1145/2934583.2934631","url":null,"abstract":"Dynamic Voltage and Frequency Scaling (DVFS) is a widely used methodology to reduce the power consumption of mobile devices. This scheme performs frequency scaling in accordance with a specific governor and sets an operating voltage to be paired with the frequency. Temperature is one of the critical parameters affecting device operation. Practically, a guard-band exists in the operating voltage to ensure safe processor operation even at the worst temperature. DVFS can be optimized in terms of operating voltage under nominal conditions. In this paper, we propose a Temperature-aware DVS (T-DVS) that aggressively reduces the voltage guard-band. We explore the opportunity of providing the minimum operating voltages for frequencies at different temperatures and realize a dynamic voltage control scheme to optimize power consumption. The effectiveness of T-DVS is validated under various thermal conditions by using multi-core application processor. We experimentally observe that T-DVS leads to voltage gain without performance degradation regardless of both thermal conditions and chip characteristics. We show by using off-the-shelf smartphones that the voltage gain achieved by the scheme results in battery lifetime increment.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132944931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Arun Joseph, Spandana Rachamalla, R. Rao, A. Haridass, P. K. Nalla
Generation of accurate IP power models requires determination of correct simulation conditions for the different input pins of the IP. Determining such a set of inputs for individual IP blocks in a design is expensive in cost and time, and is also highly error prone. Additionally, it is desirable to identify IP instances in a design, where these simulation conditions are not met. These are relevant problems in the context of modern day microprocessor designs, which are designed using a very large number of IPs, either developed in-house or sourced from external vendors. In this paper, we examine these problems in an industrial context and introduce FVCAG, a framework for enabling efficient and accurate power modelling. FVCAG enables a more thorough IP power modelling than that can be accomplished using current state of the art techniques. Experimental evaluation of the proposed framework on the standard cell library and macros used in the design of an industry class high performance microprocessor design demonstrates the accuracy and efficiency of proposed framework.
{"title":"FVCAG: A framework for formal verification driven power modeling and verification","authors":"Arun Joseph, Spandana Rachamalla, R. Rao, A. Haridass, P. K. Nalla","doi":"10.1145/2934583.2934633","DOIUrl":"https://doi.org/10.1145/2934583.2934633","url":null,"abstract":"Generation of accurate IP power models requires determination of correct simulation conditions for the different input pins of the IP. Determining such a set of inputs for individual IP blocks in a design is expensive in cost and time, and is also highly error prone. Additionally, it is desirable to identify IP instances in a design, where these simulation conditions are not met. These are relevant problems in the context of modern day microprocessor designs, which are designed using a very large number of IPs, either developed in-house or sourced from external vendors. In this paper, we examine these problems in an industrial context and introduce FVCAG, a framework for enabling efficient and accurate power modelling. FVCAG enables a more thorough IP power modelling than that can be accomplished using current state of the art techniques. Experimental evaluation of the proposed framework on the standard cell library and macros used in the design of an industry class high performance microprocessor design demonstrates the accuracy and efficiency of proposed framework.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124201142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ivan Ratković, Oscar Palomar, Milan Stanic, O. Unsal, A. Cristal, M. Valero
The need for power-efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a re-tailoring for the mobile market that they are entering now. Floating point fused multiply-add, being a power consuming functional unit, deserves special attention. Although clock-gating is a well-known method to reduce switching power in synchronous designs, there are unexplored opportunities for its application to vector processors, especially when considering active operating mode. In this research, we comprehensively identify, propose, and evaluate the most suitable clock-gating techniques for vector fused multiply-add units (VFU). These techniques ensure power savings without jeopardizing the timing. Using vector masking and vector multi-lane-aware clock-gating, we report power reductions of up to 52%, assuming active VFU operating at the peak performance. Among other findings, we observe that vector instruction-based clock-gating techniques achieve power savings for all vector floating-point instructions. We perform this research in a fully parameterizable and automated fashion using various tools at both architectural and circuit levels.
{"title":"A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques","authors":"Ivan Ratković, Oscar Palomar, Milan Stanic, O. Unsal, A. Cristal, M. Valero","doi":"10.1145/2934583.2934587","DOIUrl":"https://doi.org/10.1145/2934583.2934587","url":null,"abstract":"The need for power-efficiency is driving a rethink of design decisions in processor architectures. While vector processors succeeded in the high-performance market in the past, they need a re-tailoring for the mobile market that they are entering now. Floating point fused multiply-add, being a power consuming functional unit, deserves special attention. Although clock-gating is a well-known method to reduce switching power in synchronous designs, there are unexplored opportunities for its application to vector processors, especially when considering active operating mode. In this research, we comprehensively identify, propose, and evaluate the most suitable clock-gating techniques for vector fused multiply-add units (VFU). These techniques ensure power savings without jeopardizing the timing. Using vector masking and vector multi-lane-aware clock-gating, we report power reductions of up to 52%, assuming active VFU operating at the peak performance. Among other findings, we observe that vector instruction-based clock-gating techniques achieve power savings for all vector floating-point instructions. We perform this research in a fully parameterizable and automated fashion using various tools at both architectural and circuit levels.","PeriodicalId":142716,"journal":{"name":"Proceedings of the 2016 International Symposium on Low Power Electronics and Design","volume":"396 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123468935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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