G. Calò, G. Bellanca, Ali Emre Kaplan, F. Fuschini, M. Barbiroli, M. Bozzetti, P. Bassi, V. Petruzzelli
In this paper, we propose an integrated Vivaldi antenna, coupled to a silicon waveguide, for wireless Optical Network-on-Chip applications. On-chip wireless propagation characteristics and point-to-point link performances in homogeneous and multilayered medium are investigated and discussed as well. The proposed structure allows the implementation of wireless communication at optical frequencies and it can lead to a completely new approach in network design, allowing hybrid wireless/wired communications on the same die. This hybrid solution, in fact, can mitigate the problems related to the design and the fabrication of complex switching matrices in large networks, where long paths suffer of crosstalk and loss issues.
{"title":"Integrated Vivaldi antennas, an enabling technology for optical wireless networks on chip","authors":"G. Calò, G. Bellanca, Ali Emre Kaplan, F. Fuschini, M. Barbiroli, M. Bozzetti, P. Bassi, V. Petruzzelli","doi":"10.1145/3186608.3186609","DOIUrl":"https://doi.org/10.1145/3186608.3186609","url":null,"abstract":"In this paper, we propose an integrated Vivaldi antenna, coupled to a silicon waveguide, for wireless Optical Network-on-Chip applications. On-chip wireless propagation characteristics and point-to-point link performances in homogeneous and multilayered medium are investigated and discussed as well. The proposed structure allows the implementation of wireless communication at optical frequencies and it can lead to a completely new approach in network design, allowing hybrid wireless/wired communications on the same die. This hybrid solution, in fact, can mitigate the problems related to the design and the fabrication of complex switching matrices in large networks, where long paths suffer of crosstalk and loss issues.","PeriodicalId":147274,"journal":{"name":"Proceedings of the 3rd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126681318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Brian Lebiednik, S. Abadal, Hyoukjun Kwon, T. Krishna
With increased integration in SoCs, the Network-on-Chip (NoC) connecting of cores provides low-latency and high-throughput communication. Due to limits of scaling of electrical wires, especially for long multi-mm distances on-chip, Wireless NoC (WNoC) have shown promise. Since WNoCs can provide low-latency one-hop transfers across the chip, there has been a recent surge in research demonstrating their benefits. WNoCs provide unique security challenges that have yet been unexplored. We study the potential threat of spoofing attacks in WNoCs due to malicious hardware trojans, and introduce Veritas, a drop-in solution that detects and corrects such spoofing attacks. Exploiting the static propagation environment, Veritas associates a node to a power profile. We demonstrate that, with small area and power overheads, Veritas works across a variety of settings.
{"title":"Spoofing Prevention via RF Power Profiling in Wireless Network-on-Chip","authors":"Brian Lebiednik, S. Abadal, Hyoukjun Kwon, T. Krishna","doi":"10.1145/3186608.3186610","DOIUrl":"https://doi.org/10.1145/3186608.3186610","url":null,"abstract":"With increased integration in SoCs, the Network-on-Chip (NoC) connecting of cores provides low-latency and high-throughput communication. Due to limits of scaling of electrical wires, especially for long multi-mm distances on-chip, Wireless NoC (WNoC) have shown promise. Since WNoCs can provide low-latency one-hop transfers across the chip, there has been a recent surge in research demonstrating their benefits. WNoCs provide unique security challenges that have yet been unexplored. We study the potential threat of spoofing attacks in WNoCs due to malicious hardware trojans, and introduce Veritas, a drop-in solution that detects and corrects such spoofing attacks. Exploiting the static propagation environment, Veritas associates a node to a power profile. We demonstrate that, with small area and power overheads, Veritas works across a variety of settings.","PeriodicalId":147274,"journal":{"name":"Proceedings of the 3rd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems","volume":"1 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114017505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Here, I present recent device and system results on monolithic electronic-photonic platforms developed in partially-depleted SOI CMOS, in which photonic functions are implemented with 'zero change' to the fabrication process, and solely by way of design. This platform enables the integration of photonic components, analog and digital circuits, all on a single chip, to achieve the performance and scalability needed for optical interconnects with Terabits per second data rates for high performance computing and data center applications. The resonance-based transmitters and receivers enabled by on-chip mixed-signal resonance stabilization circuits, along with very small electrical parasitics offer high bandwidth densities and sub-pJ/bit on-chip link energy consumptions to achieve Tb/s-scale optical interconnects through WDM systems.
{"title":"Monolithic Optical Interconnects in Zero-Change CMOS","authors":"A. Atabaki","doi":"10.1145/3186608.3186612","DOIUrl":"https://doi.org/10.1145/3186608.3186612","url":null,"abstract":"Here, I present recent device and system results on monolithic electronic-photonic platforms developed in partially-depleted SOI CMOS, in which photonic functions are implemented with 'zero change' to the fabrication process, and solely by way of design. This platform enables the integration of photonic components, analog and digital circuits, all on a single chip, to achieve the performance and scalability needed for optical interconnects with Terabits per second data rates for high performance computing and data center applications. The resonance-based transmitters and receivers enabled by on-chip mixed-signal resonance stabilization circuits, along with very small electrical parasitics offer high bandwidth densities and sub-pJ/bit on-chip link energy consumptions to achieve Tb/s-scale optical interconnects through WDM systems.","PeriodicalId":147274,"journal":{"name":"Proceedings of the 3rd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126131794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Syrivelis, Andrea Reale, K. Katrinis, Christian Pinto
Disaggregation and rack-scale systems have the potential of drastically decreasing TCO and increasing utilization of cloud datacenters, while maintaining performance. While the concept of organising resources in separate pools and interconnecting them together on demand is straightforward, its materialisation can be radically different in terms of performance and scale potential. In this paper, we presenta memory bus bridge architecture which enables communication between 100s of masters and slaves in todays complex multiprocessor SoCs, that are physically intregrated in different chips and even different mainboards. The bridge tightly couples serial transceivers and a circuit network for chip-to-chip transfers. A key property of the proposed bridge architecture is that it is software-defined and thus can be configured at runtime, via a software control plane, to prepare and steer memory access transactions to remote slaves. This is particularly important because it enables datacenter orchestration tools to manage the disaggregated resource allocation. Moreover, we evaluate a bridge prototype we have build for ARM AXI4 memory bus interconnect and we discuss application-level observed performance.
{"title":"A Software-defined SoC Memory Bus Bridge Architecture for Disaggregated Computing","authors":"D. Syrivelis, Andrea Reale, K. Katrinis, Christian Pinto","doi":"10.1145/3186608.3186611","DOIUrl":"https://doi.org/10.1145/3186608.3186611","url":null,"abstract":"Disaggregation and rack-scale systems have the potential of drastically decreasing TCO and increasing utilization of cloud datacenters, while maintaining performance. While the concept of organising resources in separate pools and interconnecting them together on demand is straightforward, its materialisation can be radically different in terms of performance and scale potential. In this paper, we presenta memory bus bridge architecture which enables communication between 100s of masters and slaves in todays complex multiprocessor SoCs, that are physically intregrated in different chips and even different mainboards. The bridge tightly couples serial transceivers and a circuit network for chip-to-chip transfers. A key property of the proposed bridge architecture is that it is software-defined and thus can be configured at runtime, via a software control plane, to prepare and steer memory access transactions to remote slaves. This is particularly important because it enables datacenter orchestration tools to manage the disaggregated resource allocation. Moreover, we evaluate a bridge prototype we have build for ARM AXI4 memory bus interconnect and we discuss application-level observed performance.","PeriodicalId":147274,"journal":{"name":"Proceedings of the 3rd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122111094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sören Sonntag, J. M. G. Carrasco, J. Miguel, D. M. Gritschneder
{"title":"Proceedings of the 3rd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems","authors":"Sören Sonntag, J. M. G. Carrasco, J. Miguel, D. M. Gritschneder","doi":"10.1145/3186608","DOIUrl":"https://doi.org/10.1145/3186608","url":null,"abstract":"","PeriodicalId":147274,"journal":{"name":"Proceedings of the 3rd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116925674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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