T. Schwalb, Johannes Schmid, Tobias Gädeke, K. Müller-Glaser
Nowadays, more and more developments in the embedded systems domain are based on components and abstract models. However, while the design becomes more abstract, control and monitoring during runtime are often performed on low abstraction levels. In contrast to this low level access we present a seamless design flow for adjustment and error identification using abstract component-based models. We develop an extended metamodel to describe components and their platforms and the connection between the model and the real hardware. Furthermore, we integrate on model level platform abilities for control and especially debugging to support for example real-time recording. From a user's perspective the system is designed, controlled and monitored on model level. We discuss different methods concerning runtime control and monitoring of resource constraint systems. We demonstrate the concept's applicability based on two exemplary use cases: wireless sensor network application engineering and reconfigurable hardware development.
{"title":"Component-based models for runtime control and monitoring of embedded systems","authors":"T. Schwalb, Johannes Schmid, Tobias Gädeke, K. Müller-Glaser","doi":"10.1145/2432631.2432637","DOIUrl":"https://doi.org/10.1145/2432631.2432637","url":null,"abstract":"Nowadays, more and more developments in the embedded systems domain are based on components and abstract models. However, while the design becomes more abstract, control and monitoring during runtime are often performed on low abstraction levels. In contrast to this low level access we present a seamless design flow for adjustment and error identification using abstract component-based models. We develop an extended metamodel to describe components and their platforms and the connection between the model and the real hardware. Furthermore, we integrate on model level platform abilities for control and especially debugging to support for example real-time recording. From a user's perspective the system is designed, controlled and monitored on model level. We discuss different methods concerning runtime control and monitoring of resource constraint systems. We demonstrate the concept's applicability based on two exemplary use cases: wireless sensor network application engineering and reconfigurable hardware development.","PeriodicalId":158450,"journal":{"name":"ACES-MB '12","volume":"492 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127188737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We consider the class of embedded systems user interfaces (ES-UI). They differ from classical graphical user interfaces because they use only a limited but possibly multi-modal number of inputs and offer numerous different user interface modes. We propose the domain specific language ESUIL in order to improve the quality of ES-UI software.
{"title":"Model-based development of embedded systems' user interfaces","authors":"Jelena Barth, B. Westphal, Stephan Arlt","doi":"10.1145/2432631.2432638","DOIUrl":"https://doi.org/10.1145/2432631.2432638","url":null,"abstract":"We consider the class of embedded systems user interfaces (ES-UI). They differ from classical graphical user interfaces because they use only a limited but possibly multi-modal number of inputs and offer numerous different user interface modes. We propose the domain specific language ESUIL in order to improve the quality of ES-UI software.","PeriodicalId":158450,"journal":{"name":"ACES-MB '12","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130509684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Verification of functional and non-functional requirements throughout the design process is a cost-effective solution when compared to a build-test validation process. By using a model based design process and by describing system behavior with a formal model, model checking becomes a viable solution to perform requirement verification at early stages of the design process. This paper presents how the HiLeS ADL can be used to express the behavior of the system with a Petri Net and how to use that representation to perform system verification. HiLeS is used as a intermediate stage of a model driven automated virtual prototype design framework, in which SysML is used for capturing requirements and system modeling.
{"title":"HiLeS-T: an ADL for early requirement verification of embedded systems","authors":"Horacio Hoyos, R. Casallas, F. Jiménez","doi":"10.1145/2432631.2432633","DOIUrl":"https://doi.org/10.1145/2432631.2432633","url":null,"abstract":"Verification of functional and non-functional requirements throughout the design process is a cost-effective solution when compared to a build-test validation process. By using a model based design process and by describing system behavior with a formal model, model checking becomes a viable solution to perform requirement verification at early stages of the design process. This paper presents how the HiLeS ADL can be used to express the behavior of the system with a Petri Net and how to use that representation to perform system verification. HiLeS is used as a intermediate stage of a model driven automated virtual prototype design framework, in which SysML is used for capturing requirements and system modeling.","PeriodicalId":158450,"journal":{"name":"ACES-MB '12","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128839750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Architecture Analysis and Design Language (AADL) has been widely accepted to support the development process of Distributed Real-time and Embedded (DRE) systems and ease the tension of analyzing the systems' non-functional properties. The AADL standard prescribes the dispatching and scheduling semantics for the thread components in the system using natural language. The lack of formal semantics limits the possibility to perform formal verification of AADL specifications. The main contribution of this paper is a mapping from a substantial asynchronous subset of AADL into the TASM language, allowing us to perform resource consumption and schedulability analysis of AADL models. A small case study is presented as a validation of the usefulness of this work.
{"title":"Formal execution semantics for asynchronous constructs of AADL","authors":"Jiale Zhou, Andreas Johnsen, K. Lundqvist","doi":"10.1145/2432631.2432639","DOIUrl":"https://doi.org/10.1145/2432631.2432639","url":null,"abstract":"The Architecture Analysis and Design Language (AADL) has been widely accepted to support the development process of Distributed Real-time and Embedded (DRE) systems and ease the tension of analyzing the systems' non-functional properties. The AADL standard prescribes the dispatching and scheduling semantics for the thread components in the system using natural language. The lack of formal semantics limits the possibility to perform formal verification of AADL specifications. The main contribution of this paper is a mapping from a substantial asynchronous subset of AADL into the TASM language, allowing us to perform resource consumption and schedulability analysis of AADL models. A small case study is presented as a validation of the usefulness of this work.","PeriodicalId":158450,"journal":{"name":"ACES-MB '12","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121815223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The AUTomotive Open System ARchitecture (AUTOSAR) is the emerging standard for the development of real-time embedded automotive systems. Several tools exist that support the development as well as the analysis of AUTOSAR systems. Simulation environments use models or generated source code for testing and scenario-based simulation purposes. Unfortunately, there is a lack of methods and tools supporting the early timing analysis of AUTOSAR systems. In this work, we show how to automatically transform a given AUTOSAR architecture to an interconnected set of timed automata that represents the state-based timing behavior of the system. The derived timed automata models are used for analyzing the timing behavior in an early development stage. Furthermore, we show how to analyze the resulting timing behavior supporting abstract and incomplete AUTOSAR systems using the tool UPPAAL.
{"title":"Automatic transformation of abstract AUTOSAR architectures to timed automata","authors":"Stefan Neumann, Norman Kluge, Sebastian Wätzoldt","doi":"10.1145/2432631.2432641","DOIUrl":"https://doi.org/10.1145/2432631.2432641","url":null,"abstract":"The AUTomotive Open System ARchitecture (AUTOSAR) is the emerging standard for the development of real-time embedded automotive systems. Several tools exist that support the development as well as the analysis of AUTOSAR systems. Simulation environments use models or generated source code for testing and scenario-based simulation purposes. Unfortunately, there is a lack of methods and tools supporting the early timing analysis of AUTOSAR systems. In this work, we show how to automatically transform a given AUTOSAR architecture to an interconnected set of timed automata that represents the state-based timing behavior of the system. The derived timed automata models are used for analyzing the timing behavior in an early development stage. Furthermore, we show how to analyze the resulting timing behavior supporting abstract and incomplete AUTOSAR systems using the tool UPPAAL.","PeriodicalId":158450,"journal":{"name":"ACES-MB '12","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127809599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rania Mzid, C. Mraidha, Jean-Philippe Babau, M. Abid
One key point of Real-Time Embedded Systems development is to ensure that functional and non-functional properties (NFPs) are satisfied by the implementation. For early detection of errors, the verification of NFPs is realized at the design level. Then the design model is implemented on a Real-Time Operating System (RTOS). However, the design model could be not implementable on the target RTOS. In this paper, we propose to integrate between the design and the implementation phases, a feasibility tests step to verify whether the design model is implementable on the target RTOS and a mapping step to generate the appropriate RTOS-specific model. This two-steps approach is based on an explicit description of the platform used for verification and the RTOS which is the implementation platform. Moreover an additional verification step is needed to ensure the conformity of the implementation model to the design model with regard to NFPs.
{"title":"Real-time design models to RTOS-specific models refinement verification","authors":"Rania Mzid, C. Mraidha, Jean-Philippe Babau, M. Abid","doi":"10.1145/2432631.2432636","DOIUrl":"https://doi.org/10.1145/2432631.2432636","url":null,"abstract":"One key point of Real-Time Embedded Systems development is to ensure that functional and non-functional properties (NFPs) are satisfied by the implementation. For early detection of errors, the verification of NFPs is realized at the design level. Then the design model is implemented on a Real-Time Operating System (RTOS). However, the design model could be not implementable on the target RTOS. In this paper, we propose to integrate between the design and the implementation phases, a feasibility tests step to verify whether the design model is implementable on the target RTOS and a mapping step to generate the appropriate RTOS-specific model. This two-steps approach is based on an explicit description of the platform used for verification and the RTOS which is the implementation platform. Moreover an additional verification step is needed to ensure the conformity of the implementation model to the design model with regard to NFPs.","PeriodicalId":158450,"journal":{"name":"ACES-MB '12","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125941942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Designing system architecture is still an error-prone process and a great challenge. The development of complex embedded systems like radar systems is very cost-intensive. Therefore it is important that system architects are supported by appropriate tools. Our UML-based process focuses on validating the architecture against system requirements and analyzing the impacts of requirement or architectural changes. In this paper we present a supporting tool providing automatization possibilities for the validation process. This is a major breakthrough as it reduces the need for repetitive, time consuming and mindless validation process to be conducted manually. The tool is able to handle all the requirements, including the requirements' interconnections with one another, and increase process usability.
{"title":"Tool-supported model-driven validation process for system architectures","authors":"A. Pflüger, Wolfgang Golubski, Stefan Queins","doi":"10.1145/2432631.2432632","DOIUrl":"https://doi.org/10.1145/2432631.2432632","url":null,"abstract":"Designing system architecture is still an error-prone process and a great challenge. The development of complex embedded systems like radar systems is very cost-intensive. Therefore it is important that system architects are supported by appropriate tools. Our UML-based process focuses on validating the architecture against system requirements and analyzing the impacts of requirement or architectural changes. In this paper we present a supporting tool providing automatization possibilities for the validation process. This is a major breakthrough as it reduces the need for repetitive, time consuming and mindless validation process to be conducted manually. The tool is able to handle all the requirements, including the requirements' interconnections with one another, and increase process usability.","PeriodicalId":158450,"journal":{"name":"ACES-MB '12","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129679140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Model-based Safety Analysis (MBSA) techniques exist that ensure an increased consistency by formalising the safety analysis and allow automation of the safety calculations. With the increased acceptance of Model-based Systems Engineering (MBSE) as the new systems engineering paradigm, it seems natural to combine MBSE and MBSA. This work provides a methodology and tool support for an integrated MBSE and MBSA on one common model based on SysML which allows the systems engineers to perform an automated safety analysis to receive quick feedback on their design decisions during the system design phase.
{"title":"Automatic SysML-based safety analysis","authors":"Philipp Helle","doi":"10.1145/2432631.2432635","DOIUrl":"https://doi.org/10.1145/2432631.2432635","url":null,"abstract":"Model-based Safety Analysis (MBSA) techniques exist that ensure an increased consistency by formalising the safety analysis and allow automation of the safety calculations. With the increased acceptance of Model-based Systems Engineering (MBSE) as the new systems engineering paradigm, it seems natural to combine MBSE and MBSA. This work provides a methodology and tool support for an integrated MBSE and MBSA on one common model based on SysML which allows the systems engineers to perform an automated safety analysis to receive quick feedback on their design decisions during the system design phase.","PeriodicalId":158450,"journal":{"name":"ACES-MB '12","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127399089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Peñil, H. Posadas, Alejandro Nicolás, E. Villar
Model-driven design is very common nowadays. In this context, the UML/MARTE profile is a well-known solution for real-time, embedded system modeling. This profile enables the functional and non-functional details of the system to be modeled together. Regarding non-functional details, the profile allows certain real-time constraints to be imposed when describing the system concurrency, in order to ensure predictability. However, these constraints also limit the modeling flexibility required to evaluate different design alternatives when optimizing system performance. The paper proposes a solution for automatically synthesizing the resulting models, combining new communication semantics with standard UML/MARTE real-time management features. The UML/MARTE approach presented in this paper enables concurrency and synchronization effects to be modeled at communication points, making system exploration and implementation easier.
{"title":"Automatic synthesis from UML/MARTE models using channel semantics","authors":"P. Peñil, H. Posadas, Alejandro Nicolás, E. Villar","doi":"10.1145/2432631.2432640","DOIUrl":"https://doi.org/10.1145/2432631.2432640","url":null,"abstract":"Model-driven design is very common nowadays. In this context, the UML/MARTE profile is a well-known solution for real-time, embedded system modeling. This profile enables the functional and non-functional details of the system to be modeled together. Regarding non-functional details, the profile allows certain real-time constraints to be imposed when describing the system concurrency, in order to ensure predictability. However, these constraints also limit the modeling flexibility required to evaluate different design alternatives when optimizing system performance. The paper proposes a solution for automatically synthesizing the resulting models, combining new communication semantics with standard UML/MARTE real-time management features. The UML/MARTE approach presented in this paper enables concurrency and synchronization effects to be modeled at communication points, making system exploration and implementation easier.","PeriodicalId":158450,"journal":{"name":"ACES-MB '12","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130516097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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