Pub Date : 1995-09-13DOI: 10.1109/ISSS.1995.520623
S. Ohm, F. Kurdahi, N. Dutt, Min Xu
We present an integrated approach aimed at predicting layout area needed to implement a behavioral description for a given performance goal. Our approach is novel because: (1) it accounts for all types of RT level components (FUs, buses, registers), (2) it is highly flexible, allowing the designer to tradeoff one type of resource with another and considers dependencies between these different types, (3) it is vertically integrated to include provably accurate physical level estimators, and hence provides realistic accounting of layout effects, and (4) it uses a timing model with finer granularity, accounting for various delays in RTL datapaths. We demonstrate our technique on a variety of HLS benchmarks and show that efficient and effective design space exploration can be accomplished using this technique.
{"title":"A comprehensive estimation technique for high-level synthesis","authors":"S. Ohm, F. Kurdahi, N. Dutt, Min Xu","doi":"10.1109/ISSS.1995.520623","DOIUrl":"https://doi.org/10.1109/ISSS.1995.520623","url":null,"abstract":"We present an integrated approach aimed at predicting layout area needed to implement a behavioral description for a given performance goal. Our approach is novel because: (1) it accounts for all types of RT level components (FUs, buses, registers), (2) it is highly flexible, allowing the designer to tradeoff one type of resource with another and considers dependencies between these different types, (3) it is vertically integrated to include provably accurate physical level estimators, and hence provides realistic accounting of layout effects, and (4) it uses a timing model with finer granularity, accounting for various delays in RTL datapaths. We demonstrate our technique on a variety of HLS benchmarks and show that efficient and effective design space exploration can be accomplished using this technique.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116386119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper examines the problem of code generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm for the tasks of instruction selection, register allocation and scheduling on a class of architectures defined as the [1,/spl infin/] model. Optimality is guaranteed by sufficient conditions derived from the register transfer graph (RTG), a structural representation of the architecture which depends exclusively on the processor instruction set architecture (ISA). Experimental results using the TMS320C25 as the target processor show the efficacy of the approach.
{"title":"Optimal code generation for embedded memory non-homogeneous register architectures","authors":"G. Araújo, S. Malik","doi":"10.1145/224486.224493","DOIUrl":"https://doi.org/10.1145/224486.224493","url":null,"abstract":"This paper examines the problem of code generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm for the tasks of instruction selection, register allocation and scheduling on a class of architectures defined as the [1,/spl infin/] model. Optimality is guaranteed by sufficient conditions derived from the register transfer graph (RTG), a structural representation of the architecture which depends exclusively on the processor instruction set architecture (ISA). Experimental results using the TMS320C25 as the target processor show the efficacy of the approach.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132871634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-09-13DOI: 10.1109/ISSS.1995.520627
J. Daveau, T. B. Ismail, A. Jerraya
Communication synthesis aims to transform a system with processes that communicate via high level primitives through channels into interconnected processes that communicate via signals and share communication control. We present a new algorithm that performs binding/allocation of communication units. This algorithm makes use of a cost function to evaluate different allocation alternatives. The proposed communication synthesis approach deals with both protocol selection and interface synthesis and is based on binding/allocation of communication units. We illustrate through an example the usefulness of the algorithm for allocating automatically different protocols within the same system.
{"title":"Synthesis of system-level communication by an allocation-based approach","authors":"J. Daveau, T. B. Ismail, A. Jerraya","doi":"10.1109/ISSS.1995.520627","DOIUrl":"https://doi.org/10.1109/ISSS.1995.520627","url":null,"abstract":"Communication synthesis aims to transform a system with processes that communicate via high level primitives through channels into interconnected processes that communicate via signals and share communication control. We present a new algorithm that performs binding/allocation of communication units. This algorithm makes use of a cost function to evaluate different allocation alternatives. The proposed communication synthesis approach deals with both protocol selection and interface synthesis and is based on binding/allocation of communication units. We illustrate through an example the usefulness of the algorithm for allocating automatically different protocols within the same system.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130066474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-09-13DOI: 10.1109/ISSS.1995.520629
M. Schwiegershausen, P. Pirsch
This paper presents a system level design methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. These heterogeneous systems, consisting of dedicated as well as programmable processors, are highly suitable for performing complex schemes of image processing algorithms under real time constraints. It starts from a specification of the image processing scheme, explores the design space based on a finite set of parametrizable processor modules, and by using mixed integer linear programming as mathematical framework derives heterogeneous systems, being optimal in terms of area expense and throughput rate.
{"title":"A system level design methodology for the optimization of heterogeneous multiprocessors","authors":"M. Schwiegershausen, P. Pirsch","doi":"10.1109/ISSS.1995.520629","DOIUrl":"https://doi.org/10.1109/ISSS.1995.520629","url":null,"abstract":"This paper presents a system level design methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. These heterogeneous systems, consisting of dedicated as well as programmable processors, are highly suitable for performing complex schemes of image processing algorithms under real time constraints. It starts from a specification of the image processing scheme, explores the design space based on a finite set of parametrizable processor modules, and by using mixed integer linear programming as mathematical framework derives heterogeneous systems, being optimal in terms of area expense and throughput rate.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"76 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132156953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-09-13DOI: 10.1109/ISSS.1995.520624
S. Parameswaran, M. Parkinson, Peter L. Bartlett
Automation of the hardware/software codesign methodology brings with it the need to develop sophisticated high-level profiling tools. This paper presents a profiling tool which uses execution profiling on standard C code to obtain accurate and consistent times at the level of individual compound code sections. This tool is used in the ASP Hardware/Software Codesign project. The results from this tool show that profiling must be performed on dedicated hardware which is as close as possible to the final implementation, as opposed to a workstation.
{"title":"Profiling in the ASP codesign environment","authors":"S. Parameswaran, M. Parkinson, Peter L. Bartlett","doi":"10.1109/ISSS.1995.520624","DOIUrl":"https://doi.org/10.1109/ISSS.1995.520624","url":null,"abstract":"Automation of the hardware/software codesign methodology brings with it the need to develop sophisticated high-level profiling tools. This paper presents a profiling tool which uses execution profiling on standard C code to obtain accurate and consistent times at the level of individual compound code sections. This tool is used in the ASP Hardware/Software Codesign project. The results from this tool show that profiling must be performed on dedicated hardware which is as close as possible to the final implementation, as opposed to a workstation.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121595822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
David J. Kolson, Alexandru Nicolau, N. Dutt, Ken Kennedy
One of the challenging tasks in code generation for embedded systems is register assignment. When more live variables than registers exist, some variables are necessarily accessed from data memory. Because loops are typically executed many times and are often time-critical, good register assignment in loops is exceedingly important, since accessing data memory can degrade performance. The issue of finding an optimal register assignment to loops, one which minimizes the number of spills between registers and memory, has been open for some time. In this paper, we address this issue and present an optimal, but exponential, algorithm which assigns registers to loop bodies such that the resulting spill code is minimal. We also show that a heuristic modification performs as well as the exponential approach on typical loops from scientific code.
{"title":"Optimal register assignment to loops for embedded code generation","authors":"David J. Kolson, Alexandru Nicolau, N. Dutt, Ken Kennedy","doi":"10.1145/224486.224494","DOIUrl":"https://doi.org/10.1145/224486.224494","url":null,"abstract":"One of the challenging tasks in code generation for embedded systems is register assignment. When more live variables than registers exist, some variables are necessarily accessed from data memory. Because loops are typically executed many times and are often time-critical, good register assignment in loops is exceedingly important, since accessing data memory can degrade performance. The issue of finding an optimal register assignment to loops, one which minimizes the number of spills between registers and memory, has been open for some time. In this paper, we address this issue and present an optimal, but exponential, algorithm which assigns registers to loop bodies such that the resulting spill code is minimal. We also show that a heuristic modification performs as well as the exponential approach on typical loops from scientific code.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124958199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-09-13DOI: 10.1109/ISSS.1995.520628
J. Teich, L. Thiele, Edward A. Lee
An approach to system-level modeling and simulation of a class of heterogeneous real-time systems the timing behaviour of which can be modeled by deterministic discrete event systems is described. Examples of systems we consider are self-timed systems, synchronously clocked systems, and mixed asynchronous/synchronous systems. Our model is based on several extensions to the model of timed marked graphs. Basically, we augment this model by adding new schedule constraints such that we can express simultaneity, synchronicity, finite buffering as well as arbitrary combinations of min- and max-constraints. We prove that these extensions allow efficient timing analysis and we show how to simulate realistic systems using the Ptolemy design system.
{"title":"Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model","authors":"J. Teich, L. Thiele, Edward A. Lee","doi":"10.1109/ISSS.1995.520628","DOIUrl":"https://doi.org/10.1109/ISSS.1995.520628","url":null,"abstract":"An approach to system-level modeling and simulation of a class of heterogeneous real-time systems the timing behaviour of which can be modeled by deterministic discrete event systems is described. Examples of systems we consider are self-timed systems, synchronously clocked systems, and mixed asynchronous/synchronous systems. Our model is based on several extensions to the model of timed marked graphs. Basically, we augment this model by adding new schedule constraints such that we can express simultaneity, synchronicity, finite buffering as well as arbitrary combinations of min- and max-constraints. We prove that these extensions allow efficient timing analysis and we show how to simulate realistic systems using the Ptolemy design system.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121200502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-09-13DOI: 10.1109/ISSS.1995.520626
H. Samsom, F. Franssen, F. Catthoor, H. Man
A formal verification method is presented to verify the loop ordering of a high level transformed description against its original specification. The verification is done in an automatic way and its complexity is independent on the sizes of the loops bounds. Any practical structure of loop nests can be handled. The method is especially suited for applications in the area of speech, image and video processing, front-end telecom and numerical computing systems which exhibit many loops and complex multi-dimensional signals. The efficiency of the approach is demonstrated on several realistic examples.
{"title":"System level verification of video and image processing specifications","authors":"H. Samsom, F. Franssen, F. Catthoor, H. Man","doi":"10.1109/ISSS.1995.520626","DOIUrl":"https://doi.org/10.1109/ISSS.1995.520626","url":null,"abstract":"A formal verification method is presented to verify the loop ordering of a high level transformed description against its original specification. The verification is done in an automatic way and its complexity is independent on the sizes of the loops bounds. Any practical structure of loop nests can be handled. The method is especially suited for applications in the area of speech, image and video processing, front-end telecom and numerical computing systems which exhibit many loops and complex multi-dimensional signals. The efficiency of the approach is demonstrated on several realistic examples.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115557879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-09-13DOI: 10.1109/ISSS.1995.520612
F. Thoen, M. Cornero, G. Goossens, H. Man
Software synthesis is a new approach which focuses on the support of embedded systems without the use of operating systems. Compared to traditional design practices, a better utilization of the available time and hardware resources can be achieved, because the static information provided by the system specification is fully exploited and an application-specific solution is automatically generated. On-going research on a software synthesis approach for real-time information processing systems is presented which starts from a concurrent process system specification and tries to automate the mapping of this description to a single processor. An internal representation model which is well-suited for the support of concurrency and timing constraints is proposed, together with flexible execution models for multi-tasking with real-time constraints. The method is illustrated on a personal terminal receiver demodulator for mobile satellite communication.
{"title":"Real-time multi-tasking in software synthesis for information processing systems","authors":"F. Thoen, M. Cornero, G. Goossens, H. Man","doi":"10.1109/ISSS.1995.520612","DOIUrl":"https://doi.org/10.1109/ISSS.1995.520612","url":null,"abstract":"Software synthesis is a new approach which focuses on the support of embedded systems without the use of operating systems. Compared to traditional design practices, a better utilization of the available time and hardware resources can be achieved, because the static information provided by the system specification is fully exploited and an application-specific solution is automatically generated. On-going research on a software synthesis approach for real-time information processing systems is presented which starts from a concurrent process system specification and tries to automate the mapping of this description to a single processor. An internal representation model which is well-suited for the support of concurrency and timing constraints is proposed, together with flexible execution models for multi-tasking with real-time constraints. The method is illustrated on a personal terminal receiver demodulator for mobile satellite communication.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125106613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The increasing usage of application-specific instruction set processors (ASIPs) in audio and video telecommunications has made strong demands on the rapid availability of dedicated compilers. A rule-driven approach to code generation may have benefits over model-based approaches as the user is not confined to the capabilities supported by the model. However, the sole use of transformation rules may or may not be sufficient in optimization abilities depending on the target architecture. This paper outlines experiences with a rule-driven code generation approach for two applications in audio and video processing. The first is a controller for the VideoPhone codec at SGS-Thomson Microelectronics. The second is a VLIW (very large instruction word) processor for high-fidelity and MPEG audio at Thomson Consumer Electronic Components. The experience has shown that a rule-driven approach to compilation is applicable to both the controller and VLIW architectures; however, is limited in optimization abilities for the latter.
{"title":"Industrial experience using rule-driven retargetable code generation for multimedia applications","authors":"C. Liem, P. Paulin, M. Cornero, A. Jerraya","doi":"10.1145/224486.224499","DOIUrl":"https://doi.org/10.1145/224486.224499","url":null,"abstract":"The increasing usage of application-specific instruction set processors (ASIPs) in audio and video telecommunications has made strong demands on the rapid availability of dedicated compilers. A rule-driven approach to code generation may have benefits over model-based approaches as the user is not confined to the capabilities supported by the model. However, the sole use of transformation rules may or may not be sufficient in optimization abilities depending on the target architecture. This paper outlines experiences with a rule-driven code generation approach for two applications in audio and video processing. The first is a controller for the VideoPhone codec at SGS-Thomson Microelectronics. The second is a VLIW (very large instruction word) processor for high-fidelity and MPEG audio at Thomson Consumer Electronic Components. The experience has shown that a rule-driven approach to compilation is applicable to both the controller and VLIW architectures; however, is limited in optimization abilities for the latter.","PeriodicalId":162434,"journal":{"name":"Proceedings of the Eighth International Symposium on System Synthesis","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114385537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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