Pub Date : 2020-12-31DOI: 10.1515/9780804787321-006
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Pub Date : 2019-12-31DOI: 10.1017/9781108185738.008
P. Scholten
As 2007 drew to a close, 3D integration technology had become a very hot topic in the semiconductor industry. 3D integration articles are showing up monthly in almost all of thewell-known IC trademagazines and research journals. 3D is on the verge of competing with nano as a new technology buzz word. Is all the buzz about 3D integration justified? Researchers are well aware that buzz does not always translate into commercial success. However, in this case, as pointed out by several chapter authors, 3D integration is a very natural progression for the semiconductor industry. With everyone in agreement that Moores Law will encounter the red brick wall somewhere in the 32–22 nmnodes, the ITRS roadmapnow shows 3D integration as a key technique for achieving higher transistor integration densities. While we are awaiting the ultimate replacement for CMOS technology, 3D approaches promise to improve performance (shorter interconnects), improve yield (individual device layers made on optimized process), decrease footprint and add functionality (non-silicon functionalities) without major changes in materials or technology. Going Vertical appears to be the only logical way to go. The chapters in this handbook show that many institutes and companies have demonstrated full 3D integration processes. Several universities and institutes have also made great strides on improving individual unit operations and design and modeling routines. Figure 1 shows a map of some of the global activity in 3D integration. A large percentage of the process flows that are demonstrated early on in a technological evolution are usually feasible (i.e., work in the laboratory) but ultimately are not commercially viable, thus many of the process sequences shown in this handbook may ultimately never reach commercialization. We leave it up to you to pick the winners. Certainly recent history teaches us that manufacturing processes based on wafer-level fabrication have a comparatively favorable cost structure and performance. For most applications wafer yield and chip area issues will be problematic for full wafer stacking approaches to 3D integration. In consequence, chip-to-wafer stacking concepts utilizing known dies (KGD) only are advantageous
{"title":"Conclusions","authors":"P. Scholten","doi":"10.1017/9781108185738.008","DOIUrl":"https://doi.org/10.1017/9781108185738.008","url":null,"abstract":"As 2007 drew to a close, 3D integration technology had become a very hot topic in the semiconductor industry. 3D integration articles are showing up monthly in almost all of thewell-known IC trademagazines and research journals. 3D is on the verge of competing with nano as a new technology buzz word. Is all the buzz about 3D integration justified? Researchers are well aware that buzz does not always translate into commercial success. However, in this case, as pointed out by several chapter authors, 3D integration is a very natural progression for the semiconductor industry. With everyone in agreement that Moores Law will encounter the red brick wall somewhere in the 32–22 nmnodes, the ITRS roadmapnow shows 3D integration as a key technique for achieving higher transistor integration densities. While we are awaiting the ultimate replacement for CMOS technology, 3D approaches promise to improve performance (shorter interconnects), improve yield (individual device layers made on optimized process), decrease footprint and add functionality (non-silicon functionalities) without major changes in materials or technology. Going Vertical appears to be the only logical way to go. The chapters in this handbook show that many institutes and companies have demonstrated full 3D integration processes. Several universities and institutes have also made great strides on improving individual unit operations and design and modeling routines. Figure 1 shows a map of some of the global activity in 3D integration. A large percentage of the process flows that are demonstrated early on in a technological evolution are usually feasible (i.e., work in the laboratory) but ultimately are not commercially viable, thus many of the process sequences shown in this handbook may ultimately never reach commercialization. We leave it up to you to pick the winners. Certainly recent history teaches us that manufacturing processes based on wafer-level fabrication have a comparatively favorable cost structure and performance. For most applications wafer yield and chip area issues will be problematic for full wafer stacking approaches to 3D integration. In consequence, chip-to-wafer stacking concepts utilizing known dies (KGD) only are advantageous","PeriodicalId":165100,"journal":{"name":"Twilight of the Mission Frontier","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128022134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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