There is a critical need for design automation in micro architectural modelling and synthesis. One of the areas which lacks the necessary automation support is synthesis of instruction codes targeting various design optimality criteria. This paper aims to fill this gap by providing a formal method and software tool for synthesis of instruction codes given the description of a processor as a set of instructions. The method is based on the Conditional Partial Order Graph (CPOG) model introduced recently, which is a formalism for efficient specification and synthesis of microcontrol circuits. It describes a system as a functional composition of its behavioural scenarios, or instructions, each of them being a partial order of events. In order to distinguish instructions within a CPOG they are given different encodings represented with Boolean vectors. Size and latency of the final microcontroller significantly depends on the chosen encodings, thus efficient synthesis of instruction codes is essential. This paper presents a method for optimal encoding of a given set of partial orders so that a CPOG containing all of them has the minimum complexity, thereby leading to the smallest and fastest controller.
{"title":"Automated Synthesis of Instruction Codes in the Context of Micro-architecture Design","authors":"A. Mokhov, A. Alekseyev, A. Yakovlev","doi":"10.1109/ACSD.2010.30","DOIUrl":"https://doi.org/10.1109/ACSD.2010.30","url":null,"abstract":"There is a critical need for design automation in micro architectural modelling and synthesis. One of the areas which lacks the necessary automation support is synthesis of instruction codes targeting various design optimality criteria. This paper aims to fill this gap by providing a formal method and software tool for synthesis of instruction codes given the description of a processor as a set of instructions. The method is based on the Conditional Partial Order Graph (CPOG) model introduced recently, which is a formalism for efficient specification and synthesis of microcontrol circuits. It describes a system as a functional composition of its behavioural scenarios, or instructions, each of them being a partial order of events. In order to distinguish instructions within a CPOG they are given different encodings represented with Boolean vectors. Size and latency of the final microcontroller significantly depends on the chosen encodings, thus efficient synthesis of instruction codes is essential. This paper presents a method for optimal encoding of a given set of partial orders so that a CPOG containing all of them has the minimum complexity, thereby leading to the smallest and fastest controller.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125847788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Clos networks provide the theoretically optimal solution to build high-radix switches. This paper proposes a novel asynchronous routing algorithm for general asynchronous three-stage Clos networks. As the major sub-algorithm controlling the first two stages, the asynchronous dispatching algorithm outperforms the synchronous concurrent round-robin dispatching algorithm in behaviour level simulations. In a 32-port Clos network utilizing the asynchronous routing algorithm, paths are reserved in 6.2 ns and released in 3.9 ns.
{"title":"An Asynchronous Routing Algorithm for Clos Networks","authors":"Wei Song, D. Edwards","doi":"10.1109/ACSD.2010.12","DOIUrl":"https://doi.org/10.1109/ACSD.2010.12","url":null,"abstract":"Clos networks provide the theoretically optimal solution to build high-radix switches. This paper proposes a novel asynchronous routing algorithm for general asynchronous three-stage Clos networks. As the major sub-algorithm controlling the first two stages, the asynchronous dispatching algorithm outperforms the synchronous concurrent round-robin dispatching algorithm in behaviour level simulations. In a 32-port Clos network utilizing the asynchronous routing algorithm, paths are reserved in 6.2 ns and released in 3.9 ns.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"621 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116210989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A visual polychronous formalism called Multi-Rate Instantaneous Channel Connected Data Flow (MRICDF)was developed in [1]. In [2], a visual environment called EmCodeSyn was introduced which performs software synthesis from MRICDF models. The synthesis technique replaced clock calculus technique germane to previous polychronous approaches such as SIGNAL with a top down technique based on computing the Prime Implicates (PI) of set of Boolean constraints. This Prime Implicate based method first determines a totally ordered sequence of global synchronization points for all the computation, and then gradually determines if certain computations can synchronize less often. The sequence of global synchronization points are identified by subsequent changes in one of the signals in the system and it is called a master trigger. As opposed to bottom-up clock calculus this method can detect sequential non-implement ability faster. However, the PI computation time increases with the number of variables in the Boolean equations, which in turn increases with the size of the MRICDF network. For faster synthesis, we propose an actor elimination technique that enables reduction of the size of the PI computation problem while preserving the master trigger. Hence it provides a sound and complete abstraction technique for faster determination of sequential implement ability of an MRICDF based model.
{"title":"Faster Software Synthesis Using Actor Elimination Techniques for Polychronous Formalism","authors":"B. Jose, Jason Pribble, S. Shukla","doi":"10.1109/ACSD.2010.31","DOIUrl":"https://doi.org/10.1109/ACSD.2010.31","url":null,"abstract":"A visual polychronous formalism called Multi-Rate Instantaneous Channel Connected Data Flow (MRICDF)was developed in [1]. In [2], a visual environment called EmCodeSyn was introduced which performs software synthesis from MRICDF models. The synthesis technique replaced clock calculus technique germane to previous polychronous approaches such as SIGNAL with a top down technique based on computing the Prime Implicates (PI) of set of Boolean constraints. This Prime Implicate based method first determines a totally ordered sequence of global synchronization points for all the computation, and then gradually determines if certain computations can synchronize less often. The sequence of global synchronization points are identified by subsequent changes in one of the signals in the system and it is called a master trigger. As opposed to bottom-up clock calculus this method can detect sequential non-implement ability faster. However, the PI computation time increases with the number of variables in the Boolean equations, which in turn increases with the size of the MRICDF network. For faster synthesis, we propose an actor elimination technique that enables reduction of the size of the PI computation problem while preserving the master trigger. Hence it provides a sound and complete abstraction technique for faster determination of sequential implement ability of an MRICDF based model.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121813188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1049/iet-cdt.2010.0154
Tuomas Kuismin, Keijo Heljanko, Tommi A. Junttila
Safety properties are an important class of properties as in the industrial use of model checking a large majority of the properties to be checked are safety properties. This work presents an efficient approach to model check safety properties expressed in PSL (IEEE Std 1850 Property Specification Language), an industrial property specification language. The approach can also be used as a sound but incomplete bug hunting tool for general(non-safety) PSL properties, and it will detect exactly the finite counterexamples that are the informative bad prefixes for the PSL formulas in question. The presented technique is inspired by the temporal testers approach of Pnueli and co-authors but is aimed at finite words instead of infinite words. The new approach presented in this paper handles a larger syntactic subset of PSL safety properties than earlier translations for PSL safety subsets and has been implemented on top of the open source NuSMV 2model checker. The experimental results show the approach to be a quite competitive model checking approach when compared to a state-of-the-art implementation of PSL model checking.
{"title":"Efficient Model Checking of PSL Safety Properties","authors":"Tuomas Kuismin, Keijo Heljanko, Tommi A. Junttila","doi":"10.1049/iet-cdt.2010.0154","DOIUrl":"https://doi.org/10.1049/iet-cdt.2010.0154","url":null,"abstract":"Safety properties are an important class of properties as in the industrial use of model checking a large majority of the properties to be checked are safety properties. This work presents an efficient approach to model check safety properties expressed in PSL (IEEE Std 1850 Property Specification Language), an industrial property specification language. The approach can also be used as a sound but incomplete bug hunting tool for general(non-safety) PSL properties, and it will detect exactly the finite counterexamples that are the informative bad prefixes for the PSL formulas in question. The presented technique is inspired by the temporal testers approach of Pnueli and co-authors but is aimed at finite words instead of infinite words. The new approach presented in this paper handles a larger syntactic subset of PSL safety properties than earlier translations for PSL safety subsets and has been implemented on top of the open source NuSMV 2model checker. The experimental results show the approach to be a quite competitive model checking approach when compared to a state-of-the-art implementation of PSL model checking.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115823361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing self-timed combinational logic can be complex and expensive. This paper presents a complete synthesis flow that generates self-timed combinational networks from conventional Boolean networks. The Boolean network is partitioned into small function blocks which are then synthesised using self-timed techniques. The procedure employs relaxation optimisations to distribute the overheads associated with self-timed networks between function-blocks. Relaxation is incorporated into the function block synthesis procedures, meaning the optimisations can be applied at a much finer granularity than previously possible. The new techniques are demonstrated on a range of benchmarks showing average reduction of 5% in area, 26% in latency and 48% in energy over gate-level relaxation techniques and 17% in area, 8% in latency and 20% in energy consumption over other block-level relaxation techniques.
{"title":"A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths","authors":"W. Toms, D. A. Edwards","doi":"10.1109/ACSD.2010.29","DOIUrl":"https://doi.org/10.1109/ACSD.2010.29","url":null,"abstract":"Self-timed circuits present an attractive solution to the problem of process variation. However, implementing self-timed combinational logic can be complex and expensive. This paper presents a complete synthesis flow that generates self-timed combinational networks from conventional Boolean networks. The Boolean network is partitioned into small function blocks which are then synthesised using self-timed techniques. The procedure employs relaxation optimisations to distribute the overheads associated with self-timed networks between function-blocks. Relaxation is incorporated into the function block synthesis procedures, meaning the optimisations can be applied at a much finer granularity than previously possible. The new techniques are demonstrated on a range of benchmarks showing average reduction of 5% in area, 26% in latency and 48% in energy over gate-level relaxation techniques and 17% in area, 8% in latency and 20% in energy consumption over other block-level relaxation techniques.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125769502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Semantics of many specification languages, particularly those used in the domain of hardware, is described in terms of vector-based transition systems. In such a transition system, each macro-step transition is labeled by a vector of inputs. When performing a macro-step, several inputs may potentially change. Each macro-step can thus be decomposed in a number of micro-steps, taking one input change at a time into account. This is akin to an interleaving semantics, where a concurrent step is represented by an interleaving of its constituting components. We present criteria on vector-based transition systems, which guarantee that the next state computation is independent of the order in which these micro-steps are executed. If our criteria are satisfied by the semantic definition of a certain specification, then its state-space generation or exploration algorithm needs to only consider one representative among all possible permutations of such micro-steps. We demonstrate the applicability of our criteria to the specification of transistor netlists.
{"title":"Order-Independence of Vector-Based Transition Systems","authors":"M. Raffelsieper, M. Mousavi, H. Zantema","doi":"10.1109/ACSD.2010.24","DOIUrl":"https://doi.org/10.1109/ACSD.2010.24","url":null,"abstract":"Semantics of many specification languages, particularly those used in the domain of hardware, is described in terms of vector-based transition systems. In such a transition system, each macro-step transition is labeled by a vector of inputs. When performing a macro-step, several inputs may potentially change. Each macro-step can thus be decomposed in a number of micro-steps, taking one input change at a time into account. This is akin to an interleaving semantics, where a concurrent step is represented by an interleaving of its constituting components. We present criteria on vector-based transition systems, which guarantee that the next state computation is independent of the order in which these micro-steps are executed. If our criteria are satisfied by the semantic definition of a certain specification, then its state-space generation or exploration algorithm needs to only consider one representative among all possible permutations of such micro-steps. We demonstrate the applicability of our criteria to the specification of transistor netlists.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127584118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The synchronous model of computation divides the execution of a program into an infinite sequence of so-called macro steps, which are further divided into finitely many micro steps. Since all threads of a program are forced to run in lockstep, programmers have no means to express the independence of parallel threads, which leads to a phenomenon called over-synchronization. In this paper, we therefore propose a generalization of the synchronous model of computation by means of refined clocks, which divide a macro step into finer grained steps that themselves consist of micro steps. In particular, we present a structural operational semantics of sub clocks and prove that the internal asynchrony given by sub clocks still preserves input/output determinism.
{"title":"A Formal Semantics of Clock Refinement in Imperative Synchronous Languages","authors":"Mike Gemünde, J. Brandt, K. Schneider","doi":"10.1109/ACSD.2010.25","DOIUrl":"https://doi.org/10.1109/ACSD.2010.25","url":null,"abstract":"The synchronous model of computation divides the execution of a program into an infinite sequence of so-called macro steps, which are further divided into finitely many micro steps. Since all threads of a program are forced to run in lockstep, programmers have no means to express the independence of parallel threads, which leads to a phenomenon called over-synchronization. In this paper, we therefore propose a generalization of the synchronous model of computation by means of refined clocks, which divide a macro step into finer grained steps that themselves consist of micro steps. In particular, we present a structural operational semantics of sub clocks and prove that the internal asynchrony given by sub clocks still preserves input/output determinism.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123370670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Clock gating and operand isolation are two techniques to reduce the power consumption in state-of-the-art hardware designs. Both approaches basically follow a two-step procedure: first, they statically analyze a hardware circuit to determine irrelevant computations. Second, all parts which are responsible for these computations are replaced by others that consume less power in the average case, either by dynamically gating clocks or by isolating operands. This paper focuses on the first phase, i.e. the computation of irrelevant computation. The core of our contribution is the definition of so-called passiveness conditions for each signal x, which indicate that the value currently carried by x does not contribute to the final result of the system. After showing how our theory can be generally used in the context of clock gating and operand isolation, we classify many state-of-the-art approaches and show that they are in fact conservative approximations of our general setting. Thereby, it defines the theoretical basis for adoption of these approaches in their entirety.
{"title":"The Model Checking View to Clock Gating and Operand Isolation","authors":"J. Brandt, K. Schneider, Sumit Ahuja, S. Shukla","doi":"10.1109/ACSD.2010.22","DOIUrl":"https://doi.org/10.1109/ACSD.2010.22","url":null,"abstract":"Clock gating and operand isolation are two techniques to reduce the power consumption in state-of-the-art hardware designs. Both approaches basically follow a two-step procedure: first, they statically analyze a hardware circuit to determine irrelevant computations. Second, all parts which are responsible for these computations are replaced by others that consume less power in the average case, either by dynamically gating clocks or by isolating operands. This paper focuses on the first phase, i.e. the computation of irrelevant computation. The core of our contribution is the definition of so-called passiveness conditions for each signal x, which indicate that the value currently carried by x does not contribute to the final result of the system. After showing how our theory can be generally used in the context of clock gating and operand isolation, we classify many state-of-the-art approaches and show that they are in fact conservative approximations of our general setting. Thereby, it defines the theoretical basis for adoption of these approaches in their entirety.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116444452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Intrusion detection systems (IDS) are one way to tackle the increasing number of attacks that exploit software vulnerabilities. However, the construction of such a security system is a delicate process involving: (i) the acquisition of the monitored program behavior and its storage in a compact way, (ii) the generation of a monitor detecting deviances in the program behavior. These problems are emphasized when dealing with complex or parallel programs. This paper presents a new approach to automatically generate a dedicated and customized IDS from C sources targeting multi-threaded programs. We use Petri Nets to benefit from a formal description able to compactly describe parallel behaviors. Obtained models can then be enhanced with extra requirements such as resources usage limits or temporal execution bounds by means of observers. We illustrate the benefits of our approach on a recent class of attacks targeting web servers.
{"title":"Adaptable Intrusion Detection Systems Dedicated to Concurrent Programs: A Petri Net-Based Approach","authors":"Jean-Baptiste Voron, Clément Démoulins, F. Kordon","doi":"10.1109/ACSD.2010.32","DOIUrl":"https://doi.org/10.1109/ACSD.2010.32","url":null,"abstract":"Intrusion detection systems (IDS) are one way to tackle the increasing number of attacks that exploit software vulnerabilities. However, the construction of such a security system is a delicate process involving: (i) the acquisition of the monitored program behavior and its storage in a compact way, (ii) the generation of a monitor detecting deviances in the program behavior. These problems are emphasized when dealing with complex or parallel programs. This paper presents a new approach to automatically generate a dedicated and customized IDS from C sources targeting multi-threaded programs. We use Petri Nets to benefit from a formal description able to compactly describe parallel behaviors. Obtained models can then be enhanced with extra requirements such as resources usage limits or temporal execution bounds by means of observers. We illustrate the benefits of our approach on a recent class of attacks targeting web servers.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121940525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a formal framework to evaluate stochastic properties of MANET protocols. It captures the interplay between stochastic behavior of protocols deployed at different network layers, and the underlying dynamic topology. The link connectivity model, which implicitly models node mobility, specifies link up and down lifetimes. We use so-called constrained labeled multi-transition systems (CLMSs) to specify MANETs, transitions are annotated by network restrictions, capturing the topologies in which a transition is possible. A continuous Markov chain can be generated from a CLMS, to evaluate the performance of the corresponding MANET.
{"title":"Towards Performance Evaluation of Mobile Ad Hoc Network Protocols","authors":"F. Ghassemi, A. Movaghar, W. Fokkink","doi":"10.1109/ACSD.2010.20","DOIUrl":"https://doi.org/10.1109/ACSD.2010.20","url":null,"abstract":"We present a formal framework to evaluate stochastic properties of MANET protocols. It captures the interplay between stochastic behavior of protocols deployed at different network layers, and the underlying dynamic topology. The link connectivity model, which implicitly models node mobility, specifies link up and down lifetimes. We use so-called constrained labeled multi-transition systems (CLMSs) to specify MANETs, transitions are annotated by network restrictions, capturing the topologies in which a transition is possible. A continuous Markov chain can be generated from a CLMS, to evaluate the performance of the corresponding MANET.","PeriodicalId":169191,"journal":{"name":"2010 10th International Conference on Application of Concurrency to System Design","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125178282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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