Ken-ichi Matsumoto, Katsuro Inoue, T. Kikuno, K. Torii
An experimental evaluation is presented of SRGMs (software reliability growth models). The experimental data sets were collected from compiler construction projects completed by five university students. The SRGMs studied are the exponential model, the hyperexponential model, and S-shaped models. It is shown that the S-shaped models are superior to the exponential model in both the accuracy of estimation and the goodness of fit (as determined by the Kolmogorov-Smirnov test). It is also shown that it is possible to estimate accurately residual faults from a subset of the test results. An estimation method is proposed for the hyperexponential model. It is based on the observation that the start time for testing is different for different program modules. It is shown that this method improves the goodness of fit significantly.<>
{"title":"Experimental evaluation of software reliability growth models","authors":"Ken-ichi Matsumoto, Katsuro Inoue, T. Kikuno, K. Torii","doi":"10.1109/FTCS.1988.5313","DOIUrl":"https://doi.org/10.1109/FTCS.1988.5313","url":null,"abstract":"An experimental evaluation is presented of SRGMs (software reliability growth models). The experimental data sets were collected from compiler construction projects completed by five university students. The SRGMs studied are the exponential model, the hyperexponential model, and S-shaped models. It is shown that the S-shaped models are superior to the exponential model in both the accuracy of estimation and the goodness of fit (as determined by the Kolmogorov-Smirnov test). It is also shown that it is possible to estimate accurately residual faults from a subset of the test results. An estimation method is proposed for the hyperexponential model. It is based on the observation that the start time for testing is different for different program modules. It is shown that this method improves the goodness of fit significantly.<<ETX>>","PeriodicalId":171148,"journal":{"name":"[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130777267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A simulation-based directed search approach for generating test vectors for combinational circuits has been proposed. In this method, the search for a test vector is guided by a cost function computed by the simulator. Event-driven simulation deals with circuit delays in a very natural manner. Signal controllability information required for the cost function was incorporated in a form of logic model called the threshold-value model. These concepts are now extended to meet the needs of sequential circuit test generation. Such extensions include handling of unknown values, analysis of feedback loops, and analysis of race conditions in the threshold-value model. A threshold-value sequential test generation program, TVSET, is implemented. It automatically initializes the circuit and generates race-free tests for synchronous and asynchronous circuits.<>
{"title":"A sequential circuit test generation using threshold-value simulation","authors":"K. Cheng, V. Agrawal, E. Kuh","doi":"10.1109/FTCS.1988.5292","DOIUrl":"https://doi.org/10.1109/FTCS.1988.5292","url":null,"abstract":"A simulation-based directed search approach for generating test vectors for combinational circuits has been proposed. In this method, the search for a test vector is guided by a cost function computed by the simulator. Event-driven simulation deals with circuit delays in a very natural manner. Signal controllability information required for the cost function was incorporated in a form of logic model called the threshold-value model. These concepts are now extended to meet the needs of sequential circuit test generation. Such extensions include handling of unknown values, analysis of feedback loops, and analysis of race conditions in the threshold-value model. A threshold-value sequential test generation program, TVSET, is implemented. It automatically initializes the circuit and generates race-free tests for synchronous and asynchronous circuits.<<ETX>>","PeriodicalId":171148,"journal":{"name":"[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129597374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors introduce hypergraph as the mathematical model of multibus systems. The fault-tolerance problem of the multibus system is transformed into the connectivity problem of hypergraph. First, an important inequality related to all hypergraphs is stated and proved, and when equality takes place, the hypergraph with the best connectivity is defined. Second, to find the hypergraph with the best connectivity, BIB (balanced incomplete block) design is borrowed from combinatorics and at least W (weak) BIB is generalized. The designs obtained by this theory are better than the existing results under the same condition. The main goal of this study is to bridge these three fields: multibus system design, hypergraph, and BIB design.<>
{"title":"The connectivity of hypergraph and the design of fault-tolerant multibus systems","authors":"Tinghuai Chen, T. Kang, R. Yao","doi":"10.1109/FTCS.1988.5346","DOIUrl":"https://doi.org/10.1109/FTCS.1988.5346","url":null,"abstract":"The authors introduce hypergraph as the mathematical model of multibus systems. The fault-tolerance problem of the multibus system is transformed into the connectivity problem of hypergraph. First, an important inequality related to all hypergraphs is stated and proved, and when equality takes place, the hypergraph with the best connectivity is defined. Second, to find the hypergraph with the best connectivity, BIB (balanced incomplete block) design is borrowed from combinatorics and at least W (weak) BIB is generalized. The designs obtained by this theory are better than the existing results under the same condition. The main goal of this study is to bridge these three fields: multibus system design, hypergraph, and BIB design.<<ETX>>","PeriodicalId":171148,"journal":{"name":"[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121425077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A method based on linear feedback shift registers over finite fields is presented to generate for a natural number n a pattern sequence with minimal length detecting each m-multiple stuck-open faults for M>
{"title":"Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits","authors":"H. Wunderlich, S. Hellebrand","doi":"10.1109/FTCS.1988.5294","DOIUrl":"https://doi.org/10.1109/FTCS.1988.5294","url":null,"abstract":"A method based on linear feedback shift registers over finite fields is presented to generate for a natural number n a pattern sequence with minimal length detecting each m-multiple stuck-open faults for M<or=n. A hardware architecture is discussed generating this sequence, and for n=1 a built-in self-test (BIST) approach is presented that detects all combinations of multiple combinational and single stuck-open faults. The sequences are of minimum length, and can be produced either by software, by an external chip, or be a BIST-structure. Using the latter, the hardware overhead would be of the same magnitude as a conventional pseudorandom architecture.<<ETX>>","PeriodicalId":171148,"journal":{"name":"[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121414354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors address issues central to the design and operation of a Byzantine resilient parallel computer. Interprocessor connectivity requirements are met by treating connectivity as a resource which is shared among many processing elements, allowing flexibility in their configuration and reducing complexity. Reliability analysis results are presented which demonstrate the reduced failure probability of such a system. Redundant groups are synchronized solely by message transmissions and receptions, which also provide input data consistency and output voting. Performance analysis results are presented which quantify the temporal overhead involved in executing such fault tolerance-specific operations.<>
{"title":"Fault tolerant parallel processor architecture overview","authors":"R. Harper, J. Lala, J. Deyst","doi":"10.1109/FTCS.1988.5328","DOIUrl":"https://doi.org/10.1109/FTCS.1988.5328","url":null,"abstract":"The authors address issues central to the design and operation of a Byzantine resilient parallel computer. Interprocessor connectivity requirements are met by treating connectivity as a resource which is shared among many processing elements, allowing flexibility in their configuration and reducing complexity. Reliability analysis results are presented which demonstrate the reduced failure probability of such a system. Redundant groups are synchronized solely by message transmissions and receptions, which also provide input data consistency and output voting. Performance analysis results are presented which quantify the temporal overhead involved in executing such fault tolerance-specific operations.<<ETX>>","PeriodicalId":171148,"journal":{"name":"[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132806180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A computer architecture, FTP-AP, has been designed that can efficiently implement N-version fault-tolerant software and still tolerate random hardware failures with extremely high coverage. A unified architectural approach extends a well-known hardware fault tolerant without violating the fundamental hardware fault-tolerance design principles, and it provides a possible solution to the problem of correlated software errors.<>
{"title":"Hardware and software fault tolerance: a unified architectural approach","authors":"J. Lala, L. Alger","doi":"10.1109/FTCS.1988.5326","DOIUrl":"https://doi.org/10.1109/FTCS.1988.5326","url":null,"abstract":"A computer architecture, FTP-AP, has been designed that can efficiently implement N-version fault-tolerant software and still tolerate random hardware failures with extremely high coverage. A unified architectural approach extends a well-known hardware fault tolerant without violating the fundamental hardware fault-tolerance design principles, and it provides a possible solution to the problem of correlated software errors.<<ETX>>","PeriodicalId":171148,"journal":{"name":"[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131930535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A logic system is described which is based on images and inverse images of sets under functions designed specifically to deduce logic values in circuits under multiple fault conditions. Pairs, or larger clusters, of input vectors are analyzed in a two-phase algorithm. First, in forward propagation, the sets of possible values (images) for all lines of a diagnosed circuit are determined. Next, in backward implication, the sets of values on internal lines are deduced (inverse images) based on the observed response. Any fault producing a value that does not belong to these sets is tested unconditionally.<>
{"title":"GEMINI-a logic system for fault diagnosis based on set functions","authors":"J. Rajski","doi":"10.1109/FTCS.1988.5334","DOIUrl":"https://doi.org/10.1109/FTCS.1988.5334","url":null,"abstract":"A logic system is described which is based on images and inverse images of sets under functions designed specifically to deduce logic values in circuits under multiple fault conditions. Pairs, or larger clusters, of input vectors are analyzed in a two-phase algorithm. First, in forward propagation, the sets of possible values (images) for all lines of a diagnosed circuit are determined. Next, in backward implication, the sets of values on internal lines are deduced (inverse images) based on the observed response. Any fault producing a value that does not belong to these sets is tested unconditionally.<<ETX>>","PeriodicalId":171148,"journal":{"name":"[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123036919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors give a simple recursive procedure for designing an optimal n-unit t/r/r-diagnosable system on the basis of an optimal n'-unit t'/r'/r'-diagnosable system where t>or=t', r>or=r', and n>or=n'. This recursive procedure is shown to be of great flexibility. Furthermore, it is shown that the procedure can produce a large number of optimal hybrid-fault-diagnosable systems.<>
{"title":"A recursive procedure for optimally designing a hybrid fault diagnosable system","authors":"T. Kohda, Ken-ichi Abiru","doi":"10.1109/FTCS.1988.5331","DOIUrl":"https://doi.org/10.1109/FTCS.1988.5331","url":null,"abstract":"The authors give a simple recursive procedure for designing an optimal n-unit t/r/r-diagnosable system on the basis of an optimal n'-unit t'/r'/r'-diagnosable system where t>or=t', r>or=r', and n>or=n'. This recursive procedure is shown to be of great flexibility. Furthermore, it is shown that the procedure can produce a large number of optimal hybrid-fault-diagnosable systems.<<ETX>>","PeriodicalId":171148,"journal":{"name":"[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125370622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors develop several key theorems on Berger code partitioning on which a novel totally self-checking Berger code checker design is based. This design can handle any information length. It is shown that the design exhibits a tradeoff between the number of gates and the number of gate levels. In particular, the minimum-cost realization of the design achieves a speed improvement of approximately 50%, while the increase in the number of gates is less than 30% for information length or=15 while achieving almost the same speed improvement.<>
{"title":"The design of fast totally self-checking Berger code checkers based on Berger code partitioning","authors":"Jien-Chung Lo, S. Thanawastien","doi":"10.1109/FTCS.1988.5324","DOIUrl":"https://doi.org/10.1109/FTCS.1988.5324","url":null,"abstract":"The authors develop several key theorems on Berger code partitioning on which a novel totally self-checking Berger code checker design is based. This design can handle any information length. It is shown that the design exhibits a tradeoff between the number of gates and the number of gate levels. In particular, the minimum-cost realization of the design achieves a speed improvement of approximately 50%, while the increase in the number of gates is less than 30% for information length <or=32, compared to the design given by M.A. Marouf and A.D. Friedman (1978). The minimum-cost realization uses 30% to 40% fewer gates than the cost-effective realization of the S.J. Piestrak's design (1987) for information length I>or=15 while achieving almost the same speed improvement.<<ETX>>","PeriodicalId":171148,"journal":{"name":"[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"325 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120876846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Powell, G. Bonn, Douglas T. Seaton, P. Veríssimo, F. Waeselynck
As part of the European Strategic Programme for Research in Information Technology (ESPRIT), the Delta-4 project is seeking to define an open, fault-tolerant, distributed computing architecture. The authors present the overall Delta-4 framework for open, fault-tolerant, distributed computing systems and sketch the current implementation, which is based on a local area network with specific atomic multicasting and error-processing protocols for communicating between replicated software components. The system is used to demonstrate the various fault-tolerance techniques by a replicated database application.<>
{"title":"The Delta-4 approach to dependability in open distributed computing systems","authors":"D. Powell, G. Bonn, Douglas T. Seaton, P. Veríssimo, F. Waeselynck","doi":"10.1109/FTCS.1988.5327","DOIUrl":"https://doi.org/10.1109/FTCS.1988.5327","url":null,"abstract":"As part of the European Strategic Programme for Research in Information Technology (ESPRIT), the Delta-4 project is seeking to define an open, fault-tolerant, distributed computing architecture. The authors present the overall Delta-4 framework for open, fault-tolerant, distributed computing systems and sketch the current implementation, which is based on a local area network with specific atomic multicasting and error-processing protocols for communicating between replicated software components. The system is used to demonstrate the various fault-tolerance techniques by a replicated database application.<<ETX>>","PeriodicalId":171148,"journal":{"name":"[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116904232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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