Pub Date : 2016-11-18DOI: 10.1109/MEMCOD.2016.7797751
P. Derler, K. Ravindran, Rhishikesh Limaye
This paper proposes an extension to dataflow models with timing specifications to facilitate the construction of deterministic, platform independent, precisely timed models of software in cyber-physical systems (CPS). Dataflow models are often used to describe the software/cyber part of a CPS, owing to their succinct and analyzable representation of computation and concurrency. To capture the interaction of the cyber with the physical part, it is common practice to augment the dataflow model with nodes to represent physical sensors and actuators and handle the timing outside the dataflow model. However, the precise timing of these interactions is critical to the overall application behavior, and conventional dataflow models do not capture these timing requirements. In this work, we introduce timing configurations in dataflow models to specify when this communication between cyber and physical parts takes place. Timing specifications are derived from application requirements which are independent of the platform execution behavior. A correct implementation must fulfill the dataflow and timing requirements. This paper discusses the extension of the well-studied Synchronous Dataflow (SDF) model with timing configurations, shows how traditional SDF analysis for consistency and deadlock freedom is adapted for this model, and discusses hierarchical composition and analysis of composite SDF nodes with timing configurations. We believe that a model for the cyber part of a CPS must allow for the specification of application timing behavior as an integral part of the model. Timing extensions for dataflow models accomplish this in a natural and comprehensible manner. By illustrating timing configurations for SDF, we lay the groundwork for their application to a variety of dataflow models.
{"title":"Specification of precise timing in synchronous dataflow models","authors":"P. Derler, K. Ravindran, Rhishikesh Limaye","doi":"10.1109/MEMCOD.2016.7797751","DOIUrl":"https://doi.org/10.1109/MEMCOD.2016.7797751","url":null,"abstract":"This paper proposes an extension to dataflow models with timing specifications to facilitate the construction of deterministic, platform independent, precisely timed models of software in cyber-physical systems (CPS). Dataflow models are often used to describe the software/cyber part of a CPS, owing to their succinct and analyzable representation of computation and concurrency. To capture the interaction of the cyber with the physical part, it is common practice to augment the dataflow model with nodes to represent physical sensors and actuators and handle the timing outside the dataflow model. However, the precise timing of these interactions is critical to the overall application behavior, and conventional dataflow models do not capture these timing requirements. In this work, we introduce timing configurations in dataflow models to specify when this communication between cyber and physical parts takes place. Timing specifications are derived from application requirements which are independent of the platform execution behavior. A correct implementation must fulfill the dataflow and timing requirements. This paper discusses the extension of the well-studied Synchronous Dataflow (SDF) model with timing configurations, shows how traditional SDF analysis for consistency and deadlock freedom is adapted for this model, and discusses hierarchical composition and analysis of composite SDF nodes with timing configurations. We believe that a model for the cyber part of a CPS must allow for the specification of application timing behavior as an integral part of the model. Timing extensions for dataflow models accomplish this in a natural and comprehensible manner. By illustrating timing configurations for SDF, we lay the groundwork for their application to a variety of dataflow models.","PeriodicalId":180873,"journal":{"name":"2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124441525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-18DOI: 10.1109/MEMCOD.2016.7797753
Jalil Boudjadar, J. H. Kim, S. Nadjm-Tehrani
Despite attractiveness of multicore processors for embedded systems, the potential performance gains need to be studied in the context of real-time task scheduling and memory interference. This paper explores performance-aware schedulability of multicore systems by evaluating the performance when changing scheduling policies (as design parameters). The model-based framework we build enables analyzing the performance of multicore time-critical systems using processor-centric and memory-centric scheduling policies. The system architecture we consider consists of a set of cores with a local cache and sharing the cache level L2 and main memory (DRAM). The metrics we use to compare the performance achieved by different configurations of a system are: 1) utilization of the cores; and 2) the maximum delay per access request to shared cache and DRAM. Our framework, realized using UPPAAL, can be viewed as an engineering tool to be used during design stages to identify the scheduling policies that provide better performance for a given system while maintaining system schedulability. As a proof of concept, we analyze and compare 2 different cases studies.
{"title":"Performance-aware scheduling of multicore time-critical systems","authors":"Jalil Boudjadar, J. H. Kim, S. Nadjm-Tehrani","doi":"10.1109/MEMCOD.2016.7797753","DOIUrl":"https://doi.org/10.1109/MEMCOD.2016.7797753","url":null,"abstract":"Despite attractiveness of multicore processors for embedded systems, the potential performance gains need to be studied in the context of real-time task scheduling and memory interference. This paper explores performance-aware schedulability of multicore systems by evaluating the performance when changing scheduling policies (as design parameters). The model-based framework we build enables analyzing the performance of multicore time-critical systems using processor-centric and memory-centric scheduling policies. The system architecture we consider consists of a set of cores with a local cache and sharing the cache level L2 and main memory (DRAM). The metrics we use to compare the performance achieved by different configurations of a system are: 1) utilization of the cores; and 2) the maximum delay per access request to shared cache and DRAM. Our framework, realized using UPPAAL, can be viewed as an engineering tool to be used during design stages to identify the scheduling policies that provide better performance for a given system while maintaining system schedulability. As a proof of concept, we analyze and compare 2 different cases studies.","PeriodicalId":180873,"journal":{"name":"2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123489796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-18DOI: 10.1109/MEMCOD.2016.7797752
Farhaan Fowze, Tuba Yavuz
In this paper we extend state machine diagrams with a programming concept that is highly utilized in real software: the callback mechanism. A callback is a way to interact with a library and can be instantiated in the form of synchronous or asynchronous mode. Using callbacks speeds up software development at the expense of complicating program comprehension. Introducing the callback concept to a modeling formalism preserves structural similarity between the model and the implementation. This paper presents a formal semantics for this extended formalism to make it amenable to formal verification and concurrency synthesis and to help developers avoid implementation mistakes such as race conditions and deadlocks. We report specification, verification, and synthesis case studies on a device driver.
{"title":"Specification, verification, and synthesis using extended state machines with callbacks","authors":"Farhaan Fowze, Tuba Yavuz","doi":"10.1109/MEMCOD.2016.7797752","DOIUrl":"https://doi.org/10.1109/MEMCOD.2016.7797752","url":null,"abstract":"In this paper we extend state machine diagrams with a programming concept that is highly utilized in real software: the callback mechanism. A callback is a way to interact with a library and can be instantiated in the form of synchronous or asynchronous mode. Using callbacks speeds up software development at the expense of complicating program comprehension. Introducing the callback concept to a modeling formalism preserves structural similarity between the model and the implementation. This paper presents a formal semantics for this extended formalism to make it amenable to formal verification and concurrency synthesis and to help developers avoid implementation mistakes such as race conditions and deadlocks. We report specification, verification, and synthesis case studies on a device driver.","PeriodicalId":180873,"journal":{"name":"2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124833767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-18DOI: 10.1109/MEMCOD.2016.7797750
Judith Peters, Nils Przigoda, R. Wille, R. Drechsler
The specification of non-functional requirements, e. g., on timing forms an essential part of modern system design. Modeling languages such as MARTE/CCSL provide dedicated description means enabling engineers to formally define the ticking of the clocks to be implemented in terms of clock constraints and the actually intended timing behavior in terms of instant relations. But thus far, instant relations have only been utilized in order to monitor the correct execution of the clock constraints. In this work, we propose a methodology which, for the first time, verifies clock constraints against the given instant relations. To this end, the timing behavior is represented in terms of an automaton followed by its verification through satisfiability solvers. A case study illustrates the application of the proposed methodology.
{"title":"Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models","authors":"Judith Peters, Nils Przigoda, R. Wille, R. Drechsler","doi":"10.1109/MEMCOD.2016.7797750","DOIUrl":"https://doi.org/10.1109/MEMCOD.2016.7797750","url":null,"abstract":"The specification of non-functional requirements, e. g., on timing forms an essential part of modern system design. Modeling languages such as MARTE/CCSL provide dedicated description means enabling engineers to formally define the ticking of the clocks to be implemented in terms of clock constraints and the actually intended timing behavior in terms of instant relations. But thus far, instant relations have only been utilized in order to monitor the correct execution of the clock constraints. In this work, we propose a methodology which, for the first time, verifies clock constraints against the given instant relations. To this end, the timing behavior is represented in terms of an automaton followed by its verification through satisfiability solvers. A case study illustrates the application of the proposed methodology.","PeriodicalId":180873,"journal":{"name":"2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","volume":"70 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120907575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-18DOI: 10.1109/MEMCOD.2016.7797758
Stefan Kugele, Diego Marmsoler, Nuria Mata, K. Werther
We consider the problem of achieving a required level of confidence about safety-critical systems consisting of interacting components. Especially, we address restrictions in traditional A/G reasoning techniques which may cause false positives in contract compatibility analyses. Therefore, we introduce interface assertions, i. e., predicate logical formulae over the components' interfaces. We show how to compute interface assertions for architecture configurations based on the interface assertions of the corresponding components and show soundness and relative completeness of the method. Moreover, we introduce mode-based contracts, which - as a special kind of interface assertions - consist of dedicated assume and guarantee pairs. They provide a methodological guidance for developers and facilitate contract specification in contrast to e. g. traditional A/G reasoning. For this concept, we provide algorithms to check under-specification, over-specification, and the fulfillment of specifications. We also sketch how the checks can be operationalized using SMT solvers. Finally, an example demonstrates the approach.
{"title":"Verification of component architectures using mode-based contracts","authors":"Stefan Kugele, Diego Marmsoler, Nuria Mata, K. Werther","doi":"10.1109/MEMCOD.2016.7797758","DOIUrl":"https://doi.org/10.1109/MEMCOD.2016.7797758","url":null,"abstract":"We consider the problem of achieving a required level of confidence about safety-critical systems consisting of interacting components. Especially, we address restrictions in traditional A/G reasoning techniques which may cause false positives in contract compatibility analyses. Therefore, we introduce interface assertions, i. e., predicate logical formulae over the components' interfaces. We show how to compute interface assertions for architecture configurations based on the interface assertions of the corresponding components and show soundness and relative completeness of the method. Moreover, we introduce mode-based contracts, which - as a special kind of interface assertions - consist of dedicated assume and guarantee pairs. They provide a methodological guidance for developers and facilitate contract specification in contrast to e. g. traditional A/G reasoning. For this concept, we provide algorithms to check under-specification, over-specification, and the fulfillment of specifications. We also sketch how the checks can be operationalized using SMT solvers. Finally, an example demonstrates the approach.","PeriodicalId":180873,"journal":{"name":"2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117169319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-18DOI: 10.1109/MEMCOD.2016.7797743
Oliver Marx, Carlos Villarraga, D. Stoffel, W. Kunz
Methods of Computer Algebra have shown to be useful when formally verifying data-centric hardware designs. This has been demonstrated especially for cases where complex arithmetic computations are tightly coupled with the system's control structures at the bit level. As a consequence of current design trends, however, more and more functionality that was traditionally implemented in hardware is now shifted into the low-level software of the system. Not only control functions but also more and more arithmetic operations and other data-centric functions are involved in this shift. Motivated by this observation, it is the goal of our work to extend the scope of computer-algebraic methods from hardware to low-level software. The paper develops how hardware-dependent software can be modeled algebraically so that efficient proof procedures are possible. Our results show that also in low-level software a computer-algebraic approach can have substantial advantages over state-of-the-art SMT solving.
{"title":"A computer-algebraic approach to formal verification of data-centric low-level software","authors":"Oliver Marx, Carlos Villarraga, D. Stoffel, W. Kunz","doi":"10.1109/MEMCOD.2016.7797743","DOIUrl":"https://doi.org/10.1109/MEMCOD.2016.7797743","url":null,"abstract":"Methods of Computer Algebra have shown to be useful when formally verifying data-centric hardware designs. This has been demonstrated especially for cases where complex arithmetic computations are tightly coupled with the system's control structures at the bit level. As a consequence of current design trends, however, more and more functionality that was traditionally implemented in hardware is now shifted into the low-level software of the system. Not only control functions but also more and more arithmetic operations and other data-centric functions are involved in this shift. Motivated by this observation, it is the goal of our work to extend the scope of computer-algebraic methods from hardware to low-level software. The paper develops how hardware-dependent software can be modeled algebraically so that efficient proof procedures are possible. Our results show that also in low-level software a computer-algebraic approach can have substantial advantages over state-of-the-art SMT solving.","PeriodicalId":180873,"journal":{"name":"2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132218862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-18DOI: 10.1109/MEMCOD.2016.7797755
Peter Milder
K-means is a clustering algorithm that aims to group data into k similar clusters. The objective of the 2016 MEMOCODE Design Contest is to implement a system to efficiently partition a large set of multidimensional data using k-means. Contestants were given one month to develop a system to perform this operation, aiming to maximize performance or cost-adjusted performance. Teams were encouraged to consider a variety of computational targets including CPUs, FPGAs, and GPGPUs. The winning team, which was invited to contribute a paper describing their techniques, combined careful algorithmic and implementation optimizations using CPUs and GPUs.
k -means是一种聚类算法，旨在将数据分组到k个相似的聚类中。2016 MEMOCODE设计竞赛的目标是实现一个使用k-means对大量多维数据进行有效分区的系统。参赛者有一个月的时间来开发一个系统来执行这项操作，目的是最大化性能或成本调整后的性能。团队被鼓励考虑各种计算目标，包括cpu、fpga和gpgpu。获胜的团队被邀请撰写一篇论文，描述他们的技术，使用cpu和gpu结合了仔细的算法和实现优化。
{"title":"MEMOCODE 2016 design contest: K-means clustering","authors":"Peter Milder","doi":"10.1109/MEMCOD.2016.7797755","DOIUrl":"https://doi.org/10.1109/MEMCOD.2016.7797755","url":null,"abstract":"K-means is a clustering algorithm that aims to group data into k similar clusters. The objective of the 2016 MEMOCODE Design Contest is to implement a system to efficiently partition a large set of multidimensional data using k-means. Contestants were given one month to develop a system to perform this operation, aiming to maximize performance or cost-adjusted performance. Teams were encouraged to consider a variety of computational targets including CPUs, FPGAs, and GPGPUs. The winning team, which was invited to contribute a paper describing their techniques, combined careful algorithmic and implementation optimizations using CPUs and GPUs.","PeriodicalId":180873,"journal":{"name":"2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126044799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-18DOI: 10.1109/MEMCOD.2016.7797754
P. Banga, Atul Pai, Subhajit Roy, Mainak Chaudhuri
Given an input that can trigger a concurrency bug, only a subset of possible thread schedules satisfying certain constraints can actually cause such a bug to manifest. Recent proposals on controlled randomization of thread schedules with concrete guarantees on bug detection probabilities have opened promising avenues in this direction. However, to boost the bug detection probability, these techniques typically require a significant number of schedules to be explored. As a result, it is, in general, beneficial to accelerate the schedule space exploration of the multi-threaded programs. In this paper, we introduce Simultaneous Interleaving Exploration with Controlled Sequencing (SINECOSEQ), a generic framework that leverages the high-performance graphics processing units (GPUs) to significantly accelerate schedule space navigation of general-purpose multi-threaded programs. The SINE framework accepts POSIX compliant multi-threaded programs, instruments them to intercept all shared memory accesses, and automatically generates CUDA (Compute Unified Device Architecture) compliant code that navigates the schedule space of the input multi-threaded program on an NVIDIA GPU. Each GPU thread typically explores one schedule of the input program. The COSEQ framework decides how the schedule space is navigated by architecting the schedules on the fly. While it is straightforward to construct and navigate a different schedule on each GPU thread, the performance of the resulting technique can be very poor due to disparate pieces of codes executed by each GPU thread leading to full control divergence. In this paper, we demonstrate one application of SINECOSEQ by proposing a new GPU-friendly scheduler for accelerated concurrency testing (ACT), which is inspired by the recently proposed randomized scheduler of probabilistic concurrency testing (PCT). Compared to the state-of-the-art parallel PCT (PPCT) implementation on a twelve-core CPU, our proposal implemented on an NVIDIA Kepler K20c GPU card significantly speeds up schedule space exploration for eight multi-threaded applications and kernels drawn from the Phoenix and the PARSEC suites.
{"title":"Accelerating schedule space exploration of multi-threaded programs with GPUs","authors":"P. Banga, Atul Pai, Subhajit Roy, Mainak Chaudhuri","doi":"10.1109/MEMCOD.2016.7797754","DOIUrl":"https://doi.org/10.1109/MEMCOD.2016.7797754","url":null,"abstract":"Given an input that can trigger a concurrency bug, only a subset of possible thread schedules satisfying certain constraints can actually cause such a bug to manifest. Recent proposals on controlled randomization of thread schedules with concrete guarantees on bug detection probabilities have opened promising avenues in this direction. However, to boost the bug detection probability, these techniques typically require a significant number of schedules to be explored. As a result, it is, in general, beneficial to accelerate the schedule space exploration of the multi-threaded programs. In this paper, we introduce Simultaneous Interleaving Exploration with Controlled Sequencing (SINECOSEQ), a generic framework that leverages the high-performance graphics processing units (GPUs) to significantly accelerate schedule space navigation of general-purpose multi-threaded programs. The SINE framework accepts POSIX compliant multi-threaded programs, instruments them to intercept all shared memory accesses, and automatically generates CUDA (Compute Unified Device Architecture) compliant code that navigates the schedule space of the input multi-threaded program on an NVIDIA GPU. Each GPU thread typically explores one schedule of the input program. The COSEQ framework decides how the schedule space is navigated by architecting the schedules on the fly. While it is straightforward to construct and navigate a different schedule on each GPU thread, the performance of the resulting technique can be very poor due to disparate pieces of codes executed by each GPU thread leading to full control divergence. In this paper, we demonstrate one application of SINECOSEQ by proposing a new GPU-friendly scheduler for accelerated concurrency testing (ACT), which is inspired by the recently proposed randomized scheduler of probabilistic concurrency testing (PCT). Compared to the state-of-the-art parallel PCT (PPCT) implementation on a twelve-core CPU, our proposal implemented on an NVIDIA Kepler K20c GPU card significantly speeds up schedule space exploration for eight multi-threaded applications and kernels drawn from the Phoenix and the PARSEC suites.","PeriodicalId":180873,"journal":{"name":"2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127440320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We provide a dynamic programming algorithm for the monitoring of a fragment of Timed Propositional Temporal Logic (TPTL) specifications. This fragment of TPTL, which is more expressive than Metric Temporal Logic, is characterized by independent time variables which enable the elicitation of complex real-time requirements. For this fragment, we provide an efficient polynomial time algorithm for off-line monitoring of finite traces. Finally, we provide experimental results on a prototype implementation of our tool in order to demonstrate the feasibility of using our tool in practical applications.
{"title":"An efficient algorithm for monitoring practical TPTL specifications","authors":"Adel Dokhanchi, Bardh Hoxha, Cumhur Erkan Tuncali, Georgios Fainekos","doi":"10.1109/MEMCOD.2016.7797763","DOIUrl":"https://doi.org/10.1109/MEMCOD.2016.7797763","url":null,"abstract":"We provide a dynamic programming algorithm for the monitoring of a fragment of Timed Propositional Temporal Logic (TPTL) specifications. This fragment of TPTL, which is more expressive than Metric Temporal Logic, is characterized by independent time variables which enable the elicitation of complex real-time requirements. For this fragment, we provide an efficient polynomial time algorithm for off-line monitoring of finite traces. Finally, we provide experimental results on a prototype implementation of our tool in order to demonstrate the feasibility of using our tool in practical applications.","PeriodicalId":180873,"journal":{"name":"2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129146775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-18DOI: 10.1109/MEMCOD.2016.7797744
Tripti Jain, K. Schneider
A concentrator is a circuit with n inputs and m ≤ n outputs that can route any given subset of k ≤ m valid inputs to k of its m outputs. Concentrator circuits are important for many applications, in particular, for the design of interconnection networks. The design of concentrator circuits is however a challenging task that has already been considered in many research papers. All practical implementations aim at configuring the switches of a permutation network so that it behaves as a concentrator. In this paper, we present methods to analyze various properties of permutation networks by means of binary decision diagrams (BDDs). In particular, we can check whether it is possible to use a considered permutation network as a concentrator or even as a binary sorter. While our method can be applied to all permutation networks, we consider some particular permutation networks and verify that some of them can be used as concentrators and even as binary sorters provided that a specific permutation of the outputs is added.
{"title":"Verifying the concentration property of permutation networks by BDDs","authors":"Tripti Jain, K. Schneider","doi":"10.1109/MEMCOD.2016.7797744","DOIUrl":"https://doi.org/10.1109/MEMCOD.2016.7797744","url":null,"abstract":"A concentrator is a circuit with n inputs and m ≤ n outputs that can route any given subset of k ≤ m valid inputs to k of its m outputs. Concentrator circuits are important for many applications, in particular, for the design of interconnection networks. The design of concentrator circuits is however a challenging task that has already been considered in many research papers. All practical implementations aim at configuring the switches of a permutation network so that it behaves as a concentrator. In this paper, we present methods to analyze various properties of permutation networks by means of binary decision diagrams (BDDs). In particular, we can check whether it is possible to use a considered permutation network as a concentrator or even as a binary sorter. While our method can be applied to all permutation networks, we consider some particular permutation networks and verify that some of them can be used as concentrators and even as binary sorters provided that a specific permutation of the outputs is added.","PeriodicalId":180873,"journal":{"name":"2016 ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126455529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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