Pub Date : 2022-06-26DOI: 10.1109/DRC55272.2022.9855818
B. Shankar, K. Zeng, B. Gunning, Rafael Perez Martinez, Chuanzhe Meng, J. Flicker, A. Binder, J. Dickerson, R. Kaplar, S. Chowdhury
Power semiconductor devices encounter stressful switching conditions in power electronic circuits [1]. Therefore, avalanche capability in power devices is highly desired, and its study is extremely important for realizing robust devices. Fortunately, GaN P-N junction possess avalanche capability, making vertical GaN devices with intrinsic P-N junctions robust against breakdown [2]. Most recently, vertical GaN P-N diodes with avalanche breakdown voltage up to 6 kV were reported [3]. However, most of these studies were done under DC, and a very few have investigated the avalanche behavior under circuit-level stresses such as unclamped inductive switching (UIS) stress. We previously reported unform and robust avalanche in our in-house fabricated 1.3 kV vertical GaN-on-GaN P-N diodes [4]. In our present work we extend our study to report the observation and role of current filament (microplasma tube) formed during avalanche conditions using the 1.3 kV GaN-on-GaN vertical P-N diode under UIS stress. We infer that the robustness in avalanche increased due to the movements of current filaments relieving the thermal stress.
{"title":"Movement of Current Filaments and its Impact on Avalanche Robustness in Vertical GaN P-N diode Under UIS stress","authors":"B. Shankar, K. Zeng, B. Gunning, Rafael Perez Martinez, Chuanzhe Meng, J. Flicker, A. Binder, J. Dickerson, R. Kaplar, S. Chowdhury","doi":"10.1109/DRC55272.2022.9855818","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855818","url":null,"abstract":"Power semiconductor devices encounter stressful switching conditions in power electronic circuits [1]. Therefore, avalanche capability in power devices is highly desired, and its study is extremely important for realizing robust devices. Fortunately, GaN P-N junction possess avalanche capability, making vertical GaN devices with intrinsic P-N junctions robust against breakdown [2]. Most recently, vertical GaN P-N diodes with avalanche breakdown voltage up to 6 kV were reported [3]. However, most of these studies were done under DC, and a very few have investigated the avalanche behavior under circuit-level stresses such as unclamped inductive switching (UIS) stress. We previously reported unform and robust avalanche in our in-house fabricated 1.3 kV vertical GaN-on-GaN P-N diodes [4]. In our present work we extend our study to report the observation and role of current filament (microplasma tube) formed during avalanche conditions using the 1.3 kV GaN-on-GaN vertical P-N diode under UIS stress. We infer that the robustness in avalanche increased due to the movements of current filaments relieving the thermal stress.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"30 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125818565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-26DOI: 10.1109/DRC55272.2022.9855654
Shamiul Alam, Md. Mazharul Islam, M. S. Hossain, A. Aziz
Cryogenic (cryo) memory blocks are envisioned to be crucial components for - (i) scalable quantum computing systems with> 1000 qubits [1], and (ii) superconducting (SC) single flux quantum (SFQ) systems [2]. Decades of research has led to a whole host of cryo-memory variants (SC, non-SC, and hybrid), and more are being actively explored. Despite having such massive interest in the search for cryo-storage solutions, the design possibilities for compatible sense amplifiers (SA) remain largely unexplored. The existing approaches for cryogenic sensing are mostly agnostic to the unique properties of the memory array [3]–[5]. For example, the recently proposed SC and twistronic memories promise seamless compatibility with the cryogenic processors in terms of speed, power, and temperature range [4]–[7]. However, they rely on current-driven read operation, and necessitate voltage-based sensing. Therefore, a current-based cryo-SA [3] cannot be used for these emerging cryo-memory variants. In this work, we propose a voltage sense amplifier (VSA) for cryogenic memories utilizing the Josephson junction field effect transistor (JJFET) [8] as the primary component, and the heater cryotron (hTron) [4], [9] as an auxiliary entity. We exploit their coupled interactions to sense ultra-low (< 1 mV) voltage difference (customary for many cryo-memory technologies [4]–[7]) between the binary memory states (0/1) at/below 4 Kelvin temperature.
{"title":"Superconducting Josephson Junction FET-based Cryogenic Voltage Sense Amplifier","authors":"Shamiul Alam, Md. Mazharul Islam, M. S. Hossain, A. Aziz","doi":"10.1109/DRC55272.2022.9855654","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855654","url":null,"abstract":"Cryogenic (cryo) memory blocks are envisioned to be crucial components for - (i) scalable quantum computing systems with> 1000 qubits [1], and (ii) superconducting (SC) single flux quantum (SFQ) systems [2]. Decades of research has led to a whole host of cryo-memory variants (SC, non-SC, and hybrid), and more are being actively explored. Despite having such massive interest in the search for cryo-storage solutions, the design possibilities for compatible sense amplifiers (SA) remain largely unexplored. The existing approaches for cryogenic sensing are mostly agnostic to the unique properties of the memory array [3]–[5]. For example, the recently proposed SC and twistronic memories promise seamless compatibility with the cryogenic processors in terms of speed, power, and temperature range [4]–[7]. However, they rely on current-driven read operation, and necessitate voltage-based sensing. Therefore, a current-based cryo-SA [3] cannot be used for these emerging cryo-memory variants. In this work, we propose a voltage sense amplifier (VSA) for cryogenic memories utilizing the Josephson junction field effect transistor (JJFET) [8] as the primary component, and the heater cryotron (hTron) [4], [9] as an auxiliary entity. We exploit their coupled interactions to sense ultra-low (< 1 mV) voltage difference (customary for many cryo-memory technologies [4]–[7]) between the binary memory states (0/1) at/below 4 Kelvin temperature.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115540613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-26DOI: 10.1109/DRC55272.2022.9855800
Ying‐Chen Chen, Justin Stouffer, Favian Villanueva, Jordan Beverly
With the high demand of computing, the development of emerging memory technology with high density crossbar memory array is widely investigated for fulfilling the high demand on future applications, e.g. artificial intelligence, internet-of-things (IoT), edge computing, sensing with storage etc [1]–[3]. In the array, the sneak path current (SPC) is an inevitable problem subverting the read/write margin with the crossbar configuration, where the leakage current from neighboring cells results in operation errors. The 1T-1 R or 1 S-I M configuration with good sneak path current suppressing ability is utilized, while with high cost and fabrication complexity (Fig. 1(a) left/top). To reduce the SPC with cost efficiency, the self-rectified selector-free memory with thin film stacking fabrication is presented as the highly scalable non-volatile memory for storage and computing configurations (Fig. 1(a)). Furthermore, the RRAM can be utilized as the reprogrammable one-time programming (OTP) memory (i.e. read-only) for the embedded hardware security applications.
随着计算的高需求，为满足未来应用的高需求，如人工智能、物联网(IoT)、边缘计算、感应存储等，高密度交叉棒存储阵列的新兴存储技术的发展受到广泛研究。在阵列中，潜行路径电流(SPC)是一个不可避免的问题，它破坏了交叉条配置的读/写余量，其中来自相邻单元的泄漏电流会导致操作错误。采用了具有良好的潜行路径电流抑制能力的1t - 1r或1s - i M配置，但成本高，制造复杂(图1(a)左/上)。为了以成本效益降低SPC，采用薄膜堆叠制造的自整流无选择器存储器作为存储和计算配置的高可扩展非易失性存储器(图1(a))。此外，RRAM还可以作为嵌入式硬件安全应用的可重新编程一次性编程(OTP)存储器(即只读存储器)。
{"title":"Ambient Effects on Reprogrammable Read-only Selector-free Memory for the Embedded NVM Applications","authors":"Ying‐Chen Chen, Justin Stouffer, Favian Villanueva, Jordan Beverly","doi":"10.1109/DRC55272.2022.9855800","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855800","url":null,"abstract":"With the high demand of computing, the development of emerging memory technology with high density crossbar memory array is widely investigated for fulfilling the high demand on future applications, e.g. artificial intelligence, internet-of-things (IoT), edge computing, sensing with storage etc [1]–[3]. In the array, the sneak path current (SPC) is an inevitable problem subverting the read/write margin with the crossbar configuration, where the leakage current from neighboring cells results in operation errors. The 1T-1 R or 1 S-I M configuration with good sneak path current suppressing ability is utilized, while with high cost and fabrication complexity (Fig. 1(a) left/top). To reduce the SPC with cost efficiency, the self-rectified selector-free memory with thin film stacking fabrication is presented as the highly scalable non-volatile memory for storage and computing configurations (Fig. 1(a)). Furthermore, the RRAM can be utilized as the reprogrammable one-time programming (OTP) memory (i.e. read-only) for the embedded hardware security applications.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129552691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-26DOI: 10.1109/DRC55272.2022.9855781
Bohao Wu, S. Rakheja
With evolving research into III-nitride materials for various high-frequency applications, the ternary material ScxAl1-xN (referred to as ScAlN throughout) has emerged as an attractive candidate due to its exceptional piezoelectric effect (the piezoelectric moduli $e_{33}=9.125x+1.471(1-x)-6.625x(1-x)$ increases rapidly with an increasing $x$ [1]), ferroelectricity [2], and high spontaneous polarization [3]. Current research in ScAlN/AlN/GaN heterostructures is at a nascent stage and the potential benefits of utilizing ScAlN in high electron mobility transistors (HEMTs) are not quantified. We study the impact of alloy composition and barrier thickness on the density and the gate modulation efficiency of the two-dimensional electron gas (2DEG) in various ScAlN/AlN/GaN heterostructures (Figs. 1(a)&(b)). We identify the design constraints that must be met for this heterojunction to be used effectively within a HEMT architecture. An analytic charge-voltage (Q-V) and capacitance-voltage (C-V) model is developed and validated against Schrodinger- Poisson simulations. The analytic model is extended to 2D to account for the impact of drain bias on the channel charge for an ScAlN/AlN/GaN HEMT, and the role of channel transmission coefficient (i.e., diffusive versus quasi-ballistic (QB) transport) on Q-V and C-V is examined.
{"title":"Modeling of the Charge-Voltage Characteristics of AlScN/AlN/GaN Heterostructures","authors":"Bohao Wu, S. Rakheja","doi":"10.1109/DRC55272.2022.9855781","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855781","url":null,"abstract":"With evolving research into III-nitride materials for various high-frequency applications, the ternary material ScxAl1-xN (referred to as ScAlN throughout) has emerged as an attractive candidate due to its exceptional piezoelectric effect (the piezoelectric moduli $e_{33}=9.125x+1.471(1-x)-6.625x(1-x)$ increases rapidly with an increasing $x$ [1]), ferroelectricity [2], and high spontaneous polarization [3]. Current research in ScAlN/AlN/GaN heterostructures is at a nascent stage and the potential benefits of utilizing ScAlN in high electron mobility transistors (HEMTs) are not quantified. We study the impact of alloy composition and barrier thickness on the density and the gate modulation efficiency of the two-dimensional electron gas (2DEG) in various ScAlN/AlN/GaN heterostructures (Figs. 1(a)&(b)). We identify the design constraints that must be met for this heterojunction to be used effectively within a HEMT architecture. An analytic charge-voltage (Q-V) and capacitance-voltage (C-V) model is developed and validated against Schrodinger- Poisson simulations. The analytic model is extended to 2D to account for the impact of drain bias on the channel charge for an ScAlN/AlN/GaN HEMT, and the role of channel transmission coefficient (i.e., diffusive versus quasi-ballistic (QB) transport) on Q-V and C-V is examined.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129368907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-26DOI: 10.1109/DRC55272.2022.9855803
Anirban Kar, S. Sarker, A. Dasgupta, Y. Chauhan
Due to the better electrostatic control, semiconductor industry has already adopted gate-all-around FETs (GAAFETs) for upcoming technology nodes. Effects like sub-band quantization, threshold voltage shift, the geometry-dependent density of states (DOS) etc., are predominant in the terminal characteristics of GAAFETs due to strong geometrical confinement, which has a significant impact on both analog and RF characteristics of the device. In this paper, for the first time we demonstrate the impact of corner rounding radius $(r_{c})$ on quantum confinement effects which alter the sub-band quantization levels of the channel. We have used a 2D Schrodinger solver to obtain the sub-band energy levels and used BSIM-CMG framework to predict the effect of sub-band quantization on the terminal characteristics of the device viz. capacitances, drain currents and transconductances with respect to $r_{c}$ variations.
{"title":"Impact of Corner Rounding on Quantum Confinement in GAA Nanosheet FETs for Advanced Technology Nodes","authors":"Anirban Kar, S. Sarker, A. Dasgupta, Y. Chauhan","doi":"10.1109/DRC55272.2022.9855803","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855803","url":null,"abstract":"Due to the better electrostatic control, semiconductor industry has already adopted gate-all-around FETs (GAAFETs) for upcoming technology nodes. Effects like sub-band quantization, threshold voltage shift, the geometry-dependent density of states (DOS) etc., are predominant in the terminal characteristics of GAAFETs due to strong geometrical confinement, which has a significant impact on both analog and RF characteristics of the device. In this paper, for the first time we demonstrate the impact of corner rounding radius $(r_{c})$ on quantum confinement effects which alter the sub-band quantization levels of the channel. We have used a 2D Schrodinger solver to obtain the sub-band energy levels and used BSIM-CMG framework to predict the effect of sub-band quantization on the terminal characteristics of the device viz. capacitances, drain currents and transconductances with respect to $r_{c}$ variations.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123509106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-26DOI: 10.1109/DRC55272.2022.9855792
S. Ohmi, A. Ihara, Masakazu Tanuma, J. Pyo, Joong‐Won Shin
Ferroelectric HfO2 (Fe-HfO2) thin film has much attention for the Metal-Ferroelectrics-Si Field-Effect Transistor (MFSFET) application because of its Si compatibility [1], [2]. One of the critical issues of Fe-HfO2 is the SiO2 interfacial layer (IL) formation which degrades the memory device characteristics [1]–[3]. We have reported the ferroelectric HfN (Fe-HfN) formed on Si(100) which is crystallized in rhombohedral phase [4], [5]. The IL formation is expected to be suppressed in case of Fe-HfN compared to Fe-HfO2 from the thermodynamics point of view. In this paper, we have investigated the memory characteristics of MFSFETs utilizing Fe-HfN gate insulator. The effect of Si surface flattening process [6] was investigated to improve the interface property for analog memory application.
{"title":"MFSFET with Ferroelectric HfN for Analog Memory Application","authors":"S. Ohmi, A. Ihara, Masakazu Tanuma, J. Pyo, Joong‐Won Shin","doi":"10.1109/DRC55272.2022.9855792","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855792","url":null,"abstract":"Ferroelectric HfO2 (Fe-HfO2) thin film has much attention for the Metal-Ferroelectrics-Si Field-Effect Transistor (MFSFET) application because of its Si compatibility [1], [2]. One of the critical issues of Fe-HfO2 is the SiO2 interfacial layer (IL) formation which degrades the memory device characteristics [1]–[3]. We have reported the ferroelectric HfN (Fe-HfN) formed on Si(100) which is crystallized in rhombohedral phase [4], [5]. The IL formation is expected to be suppressed in case of Fe-HfN compared to Fe-HfO2 from the thermodynamics point of view. In this paper, we have investigated the memory characteristics of MFSFETs utilizing Fe-HfN gate insulator. The effect of Si surface flattening process [6] was investigated to improve the interface property for analog memory application.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115787436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-26DOI: 10.1109/DRC55272.2022.9855798
Chetan Kumar Dabhi, G. Pahwa, S. Salahuddin, Chenming Hu
State-of-the-art FinFETs exhibit the Gate-Induced-Drain-Leakage (GIDL) current, which cannot be attributed entirely to conventional Band-to-Band Tunneling (BTBT) physics for GIDL [1]. For the strained FinFET technology, the Trap-Assisted Tunneling (TAT) is the governing physical mechanism for most GIDL leakage due to a low gate induced vertical field in the gate-drain overlap region. This work presents the TAT-based GIDL compact model, and the developed model is validated with measurement data and TCAD simulations. The model is implemented as part of the industry-standard BSIM-CMG compact model for FinFETs.
{"title":"Compact Model for Trap Assisted Tunneling based GIDL","authors":"Chetan Kumar Dabhi, G. Pahwa, S. Salahuddin, Chenming Hu","doi":"10.1109/DRC55272.2022.9855798","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855798","url":null,"abstract":"State-of-the-art FinFETs exhibit the Gate-Induced-Drain-Leakage (GIDL) current, which cannot be attributed entirely to conventional Band-to-Band Tunneling (BTBT) physics for GIDL [1]. For the strained FinFET technology, the Trap-Assisted Tunneling (TAT) is the governing physical mechanism for most GIDL leakage due to a low gate induced vertical field in the gate-drain overlap region. This work presents the TAT-based GIDL compact model, and the developed model is validated with measurement data and TCAD simulations. The model is implemented as part of the industry-standard BSIM-CMG compact model for FinFETs.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129381077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-26DOI: 10.1109/DRC55272.2022.9855649
Zijing Zhao, Kai Xu, Jialun Liu, Wei Jiang, Hojoon Ryu, S. Rakheja, T. Low, Wenjuan Zhu
Ferroelectrics have a spontaneous electric polarization that can be reversed by the application of an external electric field, while two-dimensional (2D) materials are crystalline solids consisting of one or few layer(s) of atoms. In ferroelectric/2D heterostructures, the ferroelectric materials can provide programmable and non-volatile doping in the 2D materials, while the atomically thin body in 2D materials enables strong electrostatic control over the channel by the polarized ferroelectric metal oxides. A wide range of nanoscale devices have been developed based on ferroelectric/2D hetero structures including high-performance nonvolatile memories, steep slope transistors, programmable junctions, charge and pressure sensors, and photodiodes [1]–[4]. In recent years, van der Waals (vdW) ferroelectrics emerged, which are 2D materials with intrinsic ferroelectric order. These vdW materials can retain ferroelectricity down to 1 unit-cell thickness, have tunable bandgap, and can be grown or transferred on any substrate [5]–[7], thus enabling a new series of optoelectronic and electromechanical devices. In this talk, we will discuss our recent work in developing reconfigurable, multifunction and analog devices based on ferroelectric/2D heterostructures and vdW ferroelectric materials [8]–[14].
{"title":"Nanoscale Devices Based on Two-dimensional and Ferroelectric Materials","authors":"Zijing Zhao, Kai Xu, Jialun Liu, Wei Jiang, Hojoon Ryu, S. Rakheja, T. Low, Wenjuan Zhu","doi":"10.1109/DRC55272.2022.9855649","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855649","url":null,"abstract":"Ferroelectrics have a spontaneous electric polarization that can be reversed by the application of an external electric field, while two-dimensional (2D) materials are crystalline solids consisting of one or few layer(s) of atoms. In ferroelectric/2D heterostructures, the ferroelectric materials can provide programmable and non-volatile doping in the 2D materials, while the atomically thin body in 2D materials enables strong electrostatic control over the channel by the polarized ferroelectric metal oxides. A wide range of nanoscale devices have been developed based on ferroelectric/2D hetero structures including high-performance nonvolatile memories, steep slope transistors, programmable junctions, charge and pressure sensors, and photodiodes [1]–[4]. In recent years, van der Waals (vdW) ferroelectrics emerged, which are 2D materials with intrinsic ferroelectric order. These vdW materials can retain ferroelectricity down to 1 unit-cell thickness, have tunable bandgap, and can be grown or transferred on any substrate [5]–[7], thus enabling a new series of optoelectronic and electromechanical devices. In this talk, we will discuss our recent work in developing reconfigurable, multifunction and analog devices based on ferroelectric/2D heterostructures and vdW ferroelectric materials [8]–[14].","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126015460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-26DOI: 10.1109/DRC55272.2022.9855820
Sanghyeon Kim, Jinha Lim, J. Shim, Dae-Myeong Geum
Mid-infrared (Mid- IR) wavelength has been regarded as fingerprints for various gases, molecules, etc, motivating the development of the photonic on-chip sensors working at this spectral range. However, fabricating on-chip sensors at this wavelength has been very challenging due to the absence of the integrated photonics platform, whereas many potential platforms have been suggested and demonstrated. Furthermore, there have been not many technological options for the detector operating at room temperature because typical photon detectors suffer from thermal noise due to small photon energy at the Mid-IR wavelength.
{"title":"Ge-based Mid-infrared integrated photonics platform for Sensing","authors":"Sanghyeon Kim, Jinha Lim, J. Shim, Dae-Myeong Geum","doi":"10.1109/DRC55272.2022.9855820","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855820","url":null,"abstract":"Mid-infrared (Mid- IR) wavelength has been regarded as fingerprints for various gases, molecules, etc, motivating the development of the photonic on-chip sensors working at this spectral range. However, fabricating on-chip sensors at this wavelength has been very challenging due to the absence of the integrated photonics platform, whereas many potential platforms have been suggested and demonstrated. Furthermore, there have been not many technological options for the detector operating at room temperature because typical photon detectors suffer from thermal noise due to small photon energy at the Mid-IR wavelength.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128583549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-26DOI: 10.1109/DRC55272.2022.9855795
A. Islam, A. Miesle, M. Dietz, K. Leedy, S. Ganguli, G. Subramanyam, W. Wang, N. Sepelak, D. Dryden, S. Tetlak, K. Liddy, A. Green, K. Chabak
Ultra-wide band gap semiconductors like β-Ga2O3 undergo different high temperature processes during device fabrication. In addition, devices made with β-Ga2O3 are also promising for high temperature applications. Therefore, it is very important to study thermal stability of materials and devices, as high temperatures are known to change the integrity of the dielectric and cause diffusion of atoms across different interfaces within the device. In this article, we study the thermal stability of SiO2 and Al2O3 formed using plasma-enhanced atomic layer deposition (PEALD) on (010) Sn-doped β-Ga2O3. Our study reveals that MOSCAPs made with SiO2 maintains a breakdown strength (EBD) of > 10 MV/cm at temperatures up to 900 °C, while maintaining low leakage current at oxide electric fields Eox ≤ 5 MV/cm. In comparison, devices made with Al2O3 shows high leakage current (often starting at Eox ~ 2.5 MV/cm) and interfacial/bulk crystallization (starting at 600°C). Interface trap density (NIT) probed using multi-frequency and UV-assisted C-V measurements shows ≤ 1012 cm2 for Al2O3 and higher values for SiO2 This is the first demonstration of better thermal stability for ALD SiO2 compared to Al2O3 formed on (010) β-Ga2O3 substrates.
{"title":"Thermal stability of ALD-grown SiO2 and Al2O3 on (010) β-Ga2O3 substrates","authors":"A. Islam, A. Miesle, M. Dietz, K. Leedy, S. Ganguli, G. Subramanyam, W. Wang, N. Sepelak, D. Dryden, S. Tetlak, K. Liddy, A. Green, K. Chabak","doi":"10.1109/DRC55272.2022.9855795","DOIUrl":"https://doi.org/10.1109/DRC55272.2022.9855795","url":null,"abstract":"Ultra-wide band gap semiconductors like β-Ga<inf>2</inf>O<inf>3</inf> undergo different high temperature processes during device fabrication. In addition, devices made with β-Ga<inf>2</inf>O<inf>3</inf> are also promising for high temperature applications. Therefore, it is very important to study thermal stability of materials and devices, as high temperatures are known to change the integrity of the dielectric and cause diffusion of atoms across different interfaces within the device. In this article, we study the thermal stability of SiO<inf>2</inf> and Al<inf>2</inf>O<inf>3</inf> formed using plasma-enhanced atomic layer deposition (PEALD) on (010) Sn-doped β-Ga<inf>2</inf>O<inf>3</inf>. Our study reveals that MOSCAPs made with SiO<inf>2</inf> maintains a breakdown strength (EBD) of > 10 MV/cm at temperatures up to 900 °C, while maintaining low leakage current at oxide electric fields E<inf>ox</inf> ≤ 5 MV/cm. In comparison, devices made with Al<inf>2</inf>O<inf>3</inf> shows high leakage current (often starting at E<inf>ox</inf> ~ 2.5 MV/cm) and interfacial/bulk crystallization (starting at 600°C). Interface trap density (NIT) probed using multi-frequency and UV-assisted C-V measurements shows ≤ 10<sup>12</sup> cm<sup>2</sup> for Al<inf>2</inf>O<inf>3</inf> and higher values for SiO<inf>2</inf> This is the first demonstration of better thermal stability for ALD SiO<inf>2</inf> compared to Al<inf>2</inf>O<inf>3</inf> formed on (010) β-Ga<inf>2</inf>O<inf>3</inf> substrates.","PeriodicalId":200504,"journal":{"name":"2022 Device Research Conference (DRC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125239707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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