There is a growing need for high radix switches in data centres and high performance computing. Current computing systems are interconnected using large numbers of relatively low radix (32--48 port) switches that restrict scalability and performance, while increasing cost and management complexity. In parallel, there is a growing interest in dense rack scale computing in which a single rack can contain several thousand network nodes. To meet these demands, we recently demonstrated a flexible optical switch architecture using fast tuneable lasers and coherent receivers which scales to over 1000 ports. However, using traditional clock data recovery circuits in this or any optical packet switch results in large latency and throughput penalties due to resynchronisation on each new connection. In this talk, we will address the challenges of building a fully synchronous optical switch network, of rack-scale or greater, in which a reference clock is distributed to every node to reduce resynchronisation overhead. We will firstly present results from preliminary FPGA-based experiments demonstrating the viability of synchronising a rack scale network. We will then discuss the limitations on port count, range and bit rate which would limit the ability to build larger synchronous systems in this way.
{"title":"Enabling high performance rack-scale optical switching through global synchronisation","authors":"Kari A. Clark, Phillip Watt","doi":"10.1145/3073763.3073773","DOIUrl":"https://doi.org/10.1145/3073763.3073773","url":null,"abstract":"There is a growing need for high radix switches in data centres and high performance computing. Current computing systems are interconnected using large numbers of relatively low radix (32--48 port) switches that restrict scalability and performance, while increasing cost and management complexity. In parallel, there is a growing interest in dense rack scale computing in which a single rack can contain several thousand network nodes. To meet these demands, we recently demonstrated a flexible optical switch architecture using fast tuneable lasers and coherent receivers which scales to over 1000 ports. However, using traditional clock data recovery circuits in this or any optical packet switch results in large latency and throughput penalties due to resynchronisation on each new connection. In this talk, we will address the challenges of building a fully synchronous optical switch network, of rack-scale or greater, in which a reference clock is distributed to every node to reduce resynchronisation overhead. We will firstly present results from preliminary FPGA-based experiments demonstrating the viability of synchronising a rack scale network. We will then discuss the limitations on port count, range and bit rate which would limit the ability to build larger synchronous systems in this way.","PeriodicalId":20560,"journal":{"name":"Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems","volume":"101 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2017-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85813182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
BXI, Bull eXascale Interconnect, is the new interconnection network developed by Bull, now an Atos company for High Performance Computing. First an overview of the BXI network is presented. It is designed and optimized for HPC workloads at very large scale. The BXI network is based on the Portals 4 protocol and permits a complete offload of communication primitives in hardware, thus enabling independent progress of computation and communication. We then describe the two BXI ASIC components, the network interface and the switch, and the BXI software environment. The fabric management integrates features for monitoring, performance analysis, quick traffic re-routing and jobs isolation for performance and security. We finally explain how the Bull eXascale platform integrates BXI to build a large scale parallel system and we present some results obtained on the first BXI systems.
{"title":"BXI: designing a network for eXascale","authors":"Jean-Pierre Panziera","doi":"10.1145/3073763.3073774","DOIUrl":"https://doi.org/10.1145/3073763.3073774","url":null,"abstract":"BXI, Bull eXascale Interconnect, is the new interconnection network developed by Bull, now an Atos company for High Performance Computing. First an overview of the BXI network is presented. It is designed and optimized for HPC workloads at very large scale. The BXI network is based on the Portals 4 protocol and permits a complete offload of communication primitives in hardware, thus enabling independent progress of computation and communication. We then describe the two BXI ASIC components, the network interface and the switch, and the BXI software environment. The fabric management integrates features for monitoring, performance analysis, quick traffic re-routing and jobs isolation for performance and security. We finally explain how the Bull eXascale platform integrates BXI to build a large scale parallel system and we present some results obtained on the first BXI systems.","PeriodicalId":20560,"journal":{"name":"Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems","volume":"28 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2017-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80080935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Monobrata Debnath, Dimitris Konstantinou, C. Nicopoulos, G. Dimitrakopoulos, Wei-Ming Lin, Junghee Lee
Implementing cost effective congestion control within the Network-on-Chip (NoC) is a major design challenge. Whenever congestion awareness and/or mitigation is desired, architects typically rely on the use of adaptive routing algorithms, which aim to (intelligently) balance the traffic load throughout the NoC. Nevertheless, the hardware cost incurred by such solutions is quite considerable, since it entails the collection/propagation of traffic-related information and the provisioning of deadlock freedom guarantees. In this paper, we explore the potential of simultaneous edge and in-network traffic throttling, as a low-cost alternative to adaptive routing techniques. Without any reliance on adaptivity by the routing algorithm, combined throttling is demonstrated to yield better (in most cases) throughput improvements than state-of-the-art adaptive routing algorithms, but at a significantly lower cost.
{"title":"Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling","authors":"Monobrata Debnath, Dimitris Konstantinou, C. Nicopoulos, G. Dimitrakopoulos, Wei-Ming Lin, Junghee Lee","doi":"10.1145/3073763.3073764","DOIUrl":"https://doi.org/10.1145/3073763.3073764","url":null,"abstract":"Implementing cost effective congestion control within the Network-on-Chip (NoC) is a major design challenge. Whenever congestion awareness and/or mitigation is desired, architects typically rely on the use of adaptive routing algorithms, which aim to (intelligently) balance the traffic load throughout the NoC. Nevertheless, the hardware cost incurred by such solutions is quite considerable, since it entails the collection/propagation of traffic-related information and the provisioning of deadlock freedom guarantees. In this paper, we explore the potential of simultaneous edge and in-network traffic throttling, as a low-cost alternative to adaptive routing techniques. Without any reliance on adaptivity by the routing algorithm, combined throttling is demonstrated to yield better (in most cases) throughput improvements than state-of-the-art adaptive routing algorithms, but at a significantly lower cost.","PeriodicalId":20560,"journal":{"name":"Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems","volume":"131 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2017-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74798889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems","authors":"","doi":"10.1145/3073763","DOIUrl":"https://doi.org/10.1145/3073763","url":null,"abstract":"","PeriodicalId":20560,"journal":{"name":"Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems","volume":"42 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2017-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76329148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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