Pub Date : 1900-01-01DOI: 10.1007/978-3-030-24737-9_27
Ashok B. Mehta
{"title":"Implications of Coverage Methodology","authors":"Ashok B. Mehta","doi":"10.1007/978-3-030-24737-9_27","DOIUrl":"https://doi.org/10.1007/978-3-030-24737-9_27","url":null,"abstract":"","PeriodicalId":210866,"journal":{"name":"System Verilog Assertions and Functional Coverage","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121574717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1007/978-3-030-24737-9_15
Ashok B. Mehta
{"title":"“assume” and “restrict” for Simulation and Formal (Static Functional) Verification","authors":"Ashok B. Mehta","doi":"10.1007/978-3-030-24737-9_15","DOIUrl":"https://doi.org/10.1007/978-3-030-24737-9_15","url":null,"abstract":"","PeriodicalId":210866,"journal":{"name":"System Verilog Assertions and Functional Coverage","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130971637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1007/978-3-030-24737-9_16
Ashok B. Mehta
{"title":"Clock Domain Crossing (CDC) Verification Using Assertions","authors":"Ashok B. Mehta","doi":"10.1007/978-3-030-24737-9_16","DOIUrl":"https://doi.org/10.1007/978-3-030-24737-9_16","url":null,"abstract":"","PeriodicalId":210866,"journal":{"name":"System Verilog Assertions and Functional Coverage","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128572122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}