Pub Date : 2006-11-08DOI: 10.1109/IEMT.2006.4456432
W. Wits, R. Legtenberg, J. Mannak, B. van Zalk
A novel, integrated approach in thermal management of electronic products, based on two-phase cooling, is presented. A flat miniature heat pipe, integrated inside the laminated structure of a printed circuit board (PCB) has been developed, based on mainstream PCB fabrication processes. Hot spots on the PCB, caused by heat dissipating components, can be cooled with relatively small temperature gradients across the board. Experimental verification has shown successful heat pipe operation. The results show an equivalent thermal conductivity 11 times better compared to solid copper. The low thermal resistance values establish this concept as a promising thermal management solution for future electronic products.
{"title":"Thermal Management through In-Board Heat Pipes Manufactured using Printed Circuit Board Multilayer Technology","authors":"W. Wits, R. Legtenberg, J. Mannak, B. van Zalk","doi":"10.1109/IEMT.2006.4456432","DOIUrl":"https://doi.org/10.1109/IEMT.2006.4456432","url":null,"abstract":"A novel, integrated approach in thermal management of electronic products, based on two-phase cooling, is presented. A flat miniature heat pipe, integrated inside the laminated structure of a printed circuit board (PCB) has been developed, based on mainstream PCB fabrication processes. Hot spots on the PCB, caused by heat dissipating components, can be cooled with relatively small temperature gradients across the board. Experimental verification has shown successful heat pipe operation. The results show an equivalent thermal conductivity 11 times better compared to solid copper. The low thermal resistance values establish this concept as a promising thermal management solution for future electronic products.","PeriodicalId":212853,"journal":{"name":"2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128783212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/IEMT.2006.4456425
C. Q. Cui, K. Pun
The demand for portable, multi-functional and compact electronic products raises a great challenge to the substrate technology and related interconnection technology in electronic packaging for high density, small feature size and high performance. The requirement on the circuit density of substrate, especially, is intensive for chip scale packages (CSP) and system-in-package (SIP), where the chip size is reduced and its pin-count number is increased. Thus, the formation of small and dense via is becoming more and more important for increasing the circuit density of substrate. In this paper, ultra-fine blind via with solid Cu filled at an entry diameter of 20 mum, over the current blind via size of 50-200 mum by CO2 laser drilling, is demonstrated on polyimide based flexible substrate. Its advantages of the present innovation compared to the PTH in conventional substrate technology and micro-blind via structure in advanced high density interconnect (HDI) technology will be explored. In conclusions, the reliability of the ultra-fine blind vias has been assessed in 2-metal tape ball grid array (TBGA) and daisy chain modules at substrate level, subjected to JEDEC MST L3 at 260degC, Air to Air thermal cycle and thermal shock, T/H bias, pressure cooker test and low/high temperature storage tests, etc. In addition, the Cu fully filled ultra-fine blind via makes "landless" structure feasible on the substrate, further increasing the circuit density of substrate. In the end, the ultra-fine Cu filled blind via technology has introduced to the production in Compass for SIP, 2-metal layer chip-on-flex (COF) and multi-layer buildup flex, etc.
{"title":"Cu Fully Filled Ultra-Fine Blind Via on Flexible Substrate for High Density Interconnect","authors":"C. Q. Cui, K. Pun","doi":"10.1109/IEMT.2006.4456425","DOIUrl":"https://doi.org/10.1109/IEMT.2006.4456425","url":null,"abstract":"The demand for portable, multi-functional and compact electronic products raises a great challenge to the substrate technology and related interconnection technology in electronic packaging for high density, small feature size and high performance. The requirement on the circuit density of substrate, especially, is intensive for chip scale packages (CSP) and system-in-package (SIP), where the chip size is reduced and its pin-count number is increased. Thus, the formation of small and dense via is becoming more and more important for increasing the circuit density of substrate. In this paper, ultra-fine blind via with solid Cu filled at an entry diameter of 20 mum, over the current blind via size of 50-200 mum by CO2 laser drilling, is demonstrated on polyimide based flexible substrate. Its advantages of the present innovation compared to the PTH in conventional substrate technology and micro-blind via structure in advanced high density interconnect (HDI) technology will be explored. In conclusions, the reliability of the ultra-fine blind vias has been assessed in 2-metal tape ball grid array (TBGA) and daisy chain modules at substrate level, subjected to JEDEC MST L3 at 260degC, Air to Air thermal cycle and thermal shock, T/H bias, pressure cooker test and low/high temperature storage tests, etc. In addition, the Cu fully filled ultra-fine blind via makes \"landless\" structure feasible on the substrate, further increasing the circuit density of substrate. In the end, the ultra-fine Cu filled blind via technology has introduced to the production in Compass for SIP, 2-metal layer chip-on-flex (COF) and multi-layer buildup flex, etc.","PeriodicalId":212853,"journal":{"name":"2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123078318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/IEMT.2006.4456457
S.W. Wang, M. Yo
The drive for package thickness reduction has created new processing challenges with regards to thin wafer handling. While back grinding and die attach film (DAF) lamination are now established processes to 8 mil but dicing DAF-laminated wafers with wafer thickness of 4 mils and below is a significant challenge. This paper reports the successful introduction of 4 mil wafer dicing; with and without DAF lamination. This capability involves work in evaluating different saw parameters such as feed speed, RPM and blade types. Detail understanding in the fundamental of blade properties and characteristics is crucial to the success of this study. The results show that for thin die a dual pass saw process gives better results than a conventional single pass process. An innovative Step cut sawing is proposed. In this paper, an insight of 30 um sawing feasibility is also provided.
{"title":"4 mil DAF Die Thickness Sawing Capability Study","authors":"S.W. Wang, M. Yo","doi":"10.1109/IEMT.2006.4456457","DOIUrl":"https://doi.org/10.1109/IEMT.2006.4456457","url":null,"abstract":"The drive for package thickness reduction has created new processing challenges with regards to thin wafer handling. While back grinding and die attach film (DAF) lamination are now established processes to 8 mil but dicing DAF-laminated wafers with wafer thickness of 4 mils and below is a significant challenge. This paper reports the successful introduction of 4 mil wafer dicing; with and without DAF lamination. This capability involves work in evaluating different saw parameters such as feed speed, RPM and blade types. Detail understanding in the fundamental of blade properties and characteristics is crucial to the success of this study. The results show that for thin die a dual pass saw process gives better results than a conventional single pass process. An innovative Step cut sawing is proposed. In this paper, an insight of 30 um sawing feasibility is also provided.","PeriodicalId":212853,"journal":{"name":"2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125500209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/IEMT.2006.4456456
C. C. Theng, O. Sidek
A simulation approach is presented that allow early visibility, guidance, and analysis of clamp placement in early design stage (power template design) on a chip level complexity. The ESD robustness of product is largely attributed to the degree of correct implementation of ESD design rules in a highly complex design. Correct clamp placements is the most difficult and less guidance. Therefore, an 'intelligent' ESD clamp placement analysis is urgently needed. This tool aims to provide a preliminary guidance of clamp placement. It provides the information of where the most probable clamp placement is in the particular power template design. Since it takes into consideration the ESD ohm rules requirements during the construction of ohm sector, it would have a very high confident level that the design would not encounter much issue in the ESD resistance checkout later. Some TLP (transient line pulse) testing has proven this approach could deliver a promising ESD protection robustness. In short, the real strength of this tool is the ability to provide earlier design guidance & optimization options starting from the product concept phase (power template design stage), which allows to align ESD with all design issues on a cost and time efficient way. Without the tool, designer would need to manually calculate the resistance, rely on past experience and some assumption with nil data support which is tedious & error prone for complex design. This allows ESD design rules compliance in the early design stage, thus enhancing the approach of "correct-by-construction" on ESD design.
{"title":"Clamp Placement Optimization in Full-Chip ESD (Electro-Static-Discharge) Design","authors":"C. C. Theng, O. Sidek","doi":"10.1109/IEMT.2006.4456456","DOIUrl":"https://doi.org/10.1109/IEMT.2006.4456456","url":null,"abstract":"A simulation approach is presented that allow early visibility, guidance, and analysis of clamp placement in early design stage (power template design) on a chip level complexity. The ESD robustness of product is largely attributed to the degree of correct implementation of ESD design rules in a highly complex design. Correct clamp placements is the most difficult and less guidance. Therefore, an 'intelligent' ESD clamp placement analysis is urgently needed. This tool aims to provide a preliminary guidance of clamp placement. It provides the information of where the most probable clamp placement is in the particular power template design. Since it takes into consideration the ESD ohm rules requirements during the construction of ohm sector, it would have a very high confident level that the design would not encounter much issue in the ESD resistance checkout later. Some TLP (transient line pulse) testing has proven this approach could deliver a promising ESD protection robustness. In short, the real strength of this tool is the ability to provide earlier design guidance & optimization options starting from the product concept phase (power template design stage), which allows to align ESD with all design issues on a cost and time efficient way. Without the tool, designer would need to manually calculate the resistance, rely on past experience and some assumption with nil data support which is tedious & error prone for complex design. This allows ESD design rules compliance in the early design stage, thus enhancing the approach of \"correct-by-construction\" on ESD design.","PeriodicalId":212853,"journal":{"name":"2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122535968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/IEMT.2006.4456434
F. Abidi, S. Masood
With the increase in the chip packaging density the amount of heat generated from them has also increased considerably. Conventional cooling techniques are not well suited to solve the thermal problems that are arising as a result of this miniaturization of power microelectronic devices. We have developed a novel assembly of micro-pipe laden heat conducting substrate and thick film thermoelectric micro-cooler to deal with this issue. This paper presents the description of the novel micro-cooler fabrication technique and the results of the thermal analysis done on the micro-pipe laden substrate using the Pro/Mechanica thermal simulation package for varying performance factors.
{"title":"Thermal Analysis of Micro-Pipe Laden Substrate in Thermoelectric Micro-coolers","authors":"F. Abidi, S. Masood","doi":"10.1109/IEMT.2006.4456434","DOIUrl":"https://doi.org/10.1109/IEMT.2006.4456434","url":null,"abstract":"With the increase in the chip packaging density the amount of heat generated from them has also increased considerably. Conventional cooling techniques are not well suited to solve the thermal problems that are arising as a result of this miniaturization of power microelectronic devices. We have developed a novel assembly of micro-pipe laden heat conducting substrate and thick film thermoelectric micro-cooler to deal with this issue. This paper presents the description of the novel micro-cooler fabrication technique and the results of the thermal analysis done on the micro-pipe laden substrate using the Pro/Mechanica thermal simulation package for varying performance factors.","PeriodicalId":212853,"journal":{"name":"2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"447 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122806897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/IEMT.2006.4456454
Y. N. Zaiazmin, I. Azid
This paper presents a comparative study of MEMS piezoresistive pressure sensor simulation using two different software of ANSYS and CATIA respectively. It is aimed to investigate the feasibility of utilizing CATIA software in simulating microstructure such as MEMS device as an alternative to ANSYS simulation software. CATIA software is chosen because it is usually used in the automotive industries worldwide. Two types of diaphragm design were used in this simulation which is supported rim and without supported rim. Tetrahedral meshing with size of 0.05 mm was used in both ANSYS and CATIA simulation. Analysis of results is then made on the magnitude of x-component and Von Misses stresses on the surface of the diaphragm and also the diaphragm deflection. Based on the findings, it is concluded that CATIA software can also be used as an alternative in modeling and simulating a microstructure such as MEMS device.
{"title":"Comparison between ANSYS and CATIA Simulation Capability in Simulating Round Shape Diaphragm of MEMS Piezoresistive Pressure Sensor","authors":"Y. N. Zaiazmin, I. Azid","doi":"10.1109/IEMT.2006.4456454","DOIUrl":"https://doi.org/10.1109/IEMT.2006.4456454","url":null,"abstract":"This paper presents a comparative study of MEMS piezoresistive pressure sensor simulation using two different software of ANSYS and CATIA respectively. It is aimed to investigate the feasibility of utilizing CATIA software in simulating microstructure such as MEMS device as an alternative to ANSYS simulation software. CATIA software is chosen because it is usually used in the automotive industries worldwide. Two types of diaphragm design were used in this simulation which is supported rim and without supported rim. Tetrahedral meshing with size of 0.05 mm was used in both ANSYS and CATIA simulation. Analysis of results is then made on the magnitude of x-component and Von Misses stresses on the surface of the diaphragm and also the diaphragm deflection. Based on the findings, it is concluded that CATIA software can also be used as an alternative in modeling and simulating a microstructure such as MEMS device.","PeriodicalId":212853,"journal":{"name":"2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122828267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/IEMT.2006.4456472
T. C. Eng, G. Fonseka
The quad flat no-lead (QFN) package has gained great semiconductors market due to its advantages in thermal and electrical performance. In the further package miniaturization, challenges happened in assembly die attach and wire bonding processes, affected by extremely small and slim package size. The miniature QFN package success relied on epoxy dispensing performance and wire bonding robustness, much stringent in comparing to normal QFN. With cost as boundary condition, the new optimization methodology has helped obtaining permanent solutions in manufacturing. Leading industry in producing highly reliable, robust and cost effective miniature taped QFN, called micro ultra-thin QFN.
{"title":"QFN Miniaturization: Challenges and Solutions","authors":"T. C. Eng, G. Fonseka","doi":"10.1109/IEMT.2006.4456472","DOIUrl":"https://doi.org/10.1109/IEMT.2006.4456472","url":null,"abstract":"The quad flat no-lead (QFN) package has gained great semiconductors market due to its advantages in thermal and electrical performance. In the further package miniaturization, challenges happened in assembly die attach and wire bonding processes, affected by extremely small and slim package size. The miniature QFN package success relied on epoxy dispensing performance and wire bonding robustness, much stringent in comparing to normal QFN. With cost as boundary condition, the new optimization methodology has helped obtaining permanent solutions in manufacturing. Leading industry in producing highly reliable, robust and cost effective miniature taped QFN, called micro ultra-thin QFN.","PeriodicalId":212853,"journal":{"name":"2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129592576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/IEMT.2006.4456490
Cheong Yew Shun, Ko Bong Sang, M.J. Bin Manaf, K. Ibrahim, Zahid Jamal
This work discusses the extension of conventional method using binary masks in enhancing contact hole resolution. This can be achieved by selection of masks, mask design including choice of optical proximity correction (OPC), exposure tool, illuminator design, and resist design to do imaging process integration. The main goal is to avoid the use of PSM masks. The possible use of the binary mask prior to switching to PSM for smaller contact hole size had been evaluated by using the latest improved photoresist. A few process parameters were evaluated to achieve this objective.
{"title":"Contact Hole Process Printability Beyond 180nm On Binary Mask","authors":"Cheong Yew Shun, Ko Bong Sang, M.J. Bin Manaf, K. Ibrahim, Zahid Jamal","doi":"10.1109/IEMT.2006.4456490","DOIUrl":"https://doi.org/10.1109/IEMT.2006.4456490","url":null,"abstract":"This work discusses the extension of conventional method using binary masks in enhancing contact hole resolution. This can be achieved by selection of masks, mask design including choice of optical proximity correction (OPC), exposure tool, illuminator design, and resist design to do imaging process integration. The main goal is to avoid the use of PSM masks. The possible use of the binary mask prior to switching to PSM for smaller contact hole size had been evaluated by using the latest improved photoresist. A few process parameters were evaluated to achieve this objective.","PeriodicalId":212853,"journal":{"name":"2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121300042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/IEMT.2006.4456423
J. Liu, Yuan Yuan, Wei Gao, Y.Q. Su, R. Han, M. Han, Y.S. Lu
Market trends for PoP (package on package) developments and merits over SiP (system in package) are presented. A green VFBGA package used as bottom PoP package has been developed by applying advanced wafer thinning and dicing saw technology, low loop wire bonding technology and top gate thin molding technology. A preliminary MSL study showed good delamination performance.
介绍了PoP (package on package)的市场发展趋势及其相对于SiP (system in package)的优点。采用先进的晶圆减薄和锯切技术、低环线键合技术和顶栅薄成型技术，开发了一种绿色VFBGA封装作为底部PoP封装。初步的MSL研究显示了良好的分层性能。
{"title":"Green VFBGA Package Development for PoP Technology Study","authors":"J. Liu, Yuan Yuan, Wei Gao, Y.Q. Su, R. Han, M. Han, Y.S. Lu","doi":"10.1109/IEMT.2006.4456423","DOIUrl":"https://doi.org/10.1109/IEMT.2006.4456423","url":null,"abstract":"Market trends for PoP (package on package) developments and merits over SiP (system in package) are presented. A green VFBGA package used as bottom PoP package has been developed by applying advanced wafer thinning and dicing saw technology, low loop wire bonding technology and top gate thin molding technology. A preliminary MSL study showed good delamination performance.","PeriodicalId":212853,"journal":{"name":"2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130801992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/IEMT.2006.4456443
Dino Isa, Low Iemt Mei Fong, Lindsay Leong, Lau Yee Kuan
A vast majority of public domain MOS modeling software caters to planar devices having drain currents in the mA range. The aim of this endeavor was to modify/simplify a planar MOS model (MOS 9) in order to be able to use a genetic algorithm (GA) to optimize channel width and length for a specific drain current. After confirming that the simplified model could be used for power devices, the power MOS version of the model was then optimized for channel length and width using a genetic algorithm.
{"title":"GA optimized Power MOSFET model","authors":"Dino Isa, Low Iemt Mei Fong, Lindsay Leong, Lau Yee Kuan","doi":"10.1109/IEMT.2006.4456443","DOIUrl":"https://doi.org/10.1109/IEMT.2006.4456443","url":null,"abstract":"A vast majority of public domain MOS modeling software caters to planar devices having drain currents in the mA range. The aim of this endeavor was to modify/simplify a planar MOS model (MOS 9) in order to be able to use a genetic algorithm (GA) to optimize channel width and length for a specific drain current. After confirming that the simplified model could be used for power devices, the power MOS version of the model was then optimized for channel length and width using a genetic algorithm.","PeriodicalId":212853,"journal":{"name":"2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131141231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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