Pub Date : 2003-06-24DOI: 10.1109/MEMCOD.2003.1210113
G. Micheli
New opportunities and challenges in system design are direct consequences of the progress in semiconductor technologies, and are due to the extremely small nature of electronic devices, the extremely large complexity of systems, and the new, unchartered territory set by novel technologies. Reliable on-chip communication will require viewing routing wires as information channels, and systems as micro-networks of components. Signal transmission will face an increasingly more noisy environment, where noise abstracts undesirable effects such as timing variations, cross-talk and interference. Techniques borrowed from networking will be applicable at the chip level, to provide reliable communication over unreliable physical channels. Information encoding, packetization and routing will provide us with a new facet of design, to support reliable data transfer in a noisy environment.
{"title":"Robust system design with uncertain information","authors":"G. Micheli","doi":"10.1109/MEMCOD.2003.1210113","DOIUrl":"https://doi.org/10.1109/MEMCOD.2003.1210113","url":null,"abstract":"New opportunities and challenges in system design are direct consequences of the progress in semiconductor technologies, and are due to the extremely small nature of electronic devices, the extremely large complexity of systems, and the new, unchartered territory set by novel technologies. Reliable on-chip communication will require viewing routing wires as information channels, and systems as micro-networks of components. Signal transmission will face an increasingly more noisy environment, where noise abstracts undesirable effects such as timing variations, cross-talk and interference. Techniques borrowed from networking will be applicable at the chip level, to provide reliable communication over unreliable physical channels. Information encoding, packetization and routing will provide us with a new facet of design, to support reliable data transfer in a noisy environment.","PeriodicalId":213762,"journal":{"name":"First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125167905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-24DOI: 10.1109/MEMCOD.2003.1210086
S. Stuijk, T. Basten
We present a concurrency model that allows reasoning about concurrency in executable specifications. The model mainly focuses on data-flow and streaming applications and at task-level concurrency. The aim of the model is to provide insight in concurrency bottlenecks in an application and to provide support for performing implementation independent concurrency optimization.
{"title":"Analyzing concurrency in computational networks","authors":"S. Stuijk, T. Basten","doi":"10.1109/MEMCOD.2003.1210086","DOIUrl":"https://doi.org/10.1109/MEMCOD.2003.1210086","url":null,"abstract":"We present a concurrency model that allows reasoning about concurrency in executable specifications. The model mainly focuses on data-flow and streaming applications and at task-level concurrency. The aim of the model is to provide insight in concurrency bottlenecks in an application and to provide support for performing implementation independent concurrency optimization.","PeriodicalId":213762,"journal":{"name":"First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128151625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-24DOI: 10.1109/MEMCOD.2003.1210091
M. Contensin, L. Pierre
The purpose of this paper is the formal verification of temporal properties of system-level descriptions that include both a control part, which corresponds to a finite set of symbolic states, and a data path with numeric variables. Keeping these variables under their numeric form, without assuming any encoding, induces an infinite state space. We propose a combination of a model-checker for the modal /spl nu/-calculus with the theorem prover ACL2. Due to the induction mechanism of ACL2, this approach allows to consider the infinite state space without having to appeal to reduction techniques. Two simple but significant examples illustrate our results.
{"title":"Combining ACL2 and a /spl nu/-calculus model-checker to verify system-level designs","authors":"M. Contensin, L. Pierre","doi":"10.1109/MEMCOD.2003.1210091","DOIUrl":"https://doi.org/10.1109/MEMCOD.2003.1210091","url":null,"abstract":"The purpose of this paper is the formal verification of temporal properties of system-level descriptions that include both a control part, which corresponds to a finite set of symbolic states, and a data path with numeric variables. Keeping these variables under their numeric form, without assuming any encoding, induces an infinite state space. We propose a combination of a model-checker for the modal /spl nu/-calculus with the theorem prover ACL2. Due to the induction mechanism of ACL2, this approach allows to consider the infinite state space without having to appeal to reduction techniques. Two simple but significant examples illustrate our results.","PeriodicalId":213762,"journal":{"name":"First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133181612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-24DOI: 10.1109/MEMCOD.2003.1210100
T. Schüle, K. Schneider
In this paper, we present a technique for determining tight bounds on the execution time of assembler programs. Thus, our method is independent of the design flow, but takes into account the target architecture to obtain accurate estimates. The key idea is to compute the maximal number of executed instructions by means of symbolic simulation. To this end, we utilize a slight extension of Presburger arithmetic that can be translated to finite automata. Finite automata are an efficient data structure for symbolically traversing the state space of a program.
{"title":"Exact runtime analysis using automata-based symbolic simulation","authors":"T. Schüle, K. Schneider","doi":"10.1109/MEMCOD.2003.1210100","DOIUrl":"https://doi.org/10.1109/MEMCOD.2003.1210100","url":null,"abstract":"In this paper, we present a technique for determining tight bounds on the execution time of assembler programs. Thus, our method is independent of the design flow, but takes into account the target architecture to obtain accurate estimates. The key idea is to compute the maximal number of executed instructions by means of symbolic simulation. To this end, we utilize a slight extension of Presburger arithmetic that can be translated to finite automata. Finite automata are an efficient data structure for symbolically traversing the state space of a program.","PeriodicalId":213762,"journal":{"name":"First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134491305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-24DOI: 10.1201/9781420011746.ch32
M. Broy
Today, in general, software is embedded, distributed onto networks and structured into logical components that interact asynchronously. We study fundamental models of composed software systems and their properties, identify and describe various basic views, and show how they are related. We concentrate on models of composed systems that interact by message exchange. We consider, in particular, models of data, states, interfaces, hierarchical composed systems, and processes. We study relationships by abstraction and refinement as well as forms of composition and modularity. In particular, we introduce a comprehensive mathematical model for composed systems, its views and their relationships.
{"title":"Modular hierarchies of models for embedded systems","authors":"M. Broy","doi":"10.1201/9781420011746.ch32","DOIUrl":"https://doi.org/10.1201/9781420011746.ch32","url":null,"abstract":"Today, in general, software is embedded, distributed onto networks and structured into logical components that interact asynchronously. We study fundamental models of composed software systems and their properties, identify and describe various basic views, and show how they are related. We concentrate on models of composed systems that interact by message exchange. We consider, in particular, models of data, states, interfaces, hierarchical composed systems, and processes. We study relationships by abstraction and refinement as well as forms of composition and modularity. In particular, we introduce a comprehensive mathematical model for composed systems, its views and their relationships.","PeriodicalId":213762,"journal":{"name":"First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127123966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-24DOI: 10.1109/MEMCOD.2003.1210095
F. Bellegarde, C. Charlet, O. Kouchnarenko
In this paper, we present a refinement verification for a class of parameterized systems. These systems are composed of an arbitrary number of similar processes. As in (Abdulla et al., 199) we represent the states by regular languages and the transitions by transducers over regular languages. If we can compute a symbolic model by acceleration of the actions, then we can also verify a refinement relation R between the symbolic models. We show that, under some conditions, if R is verified between two symbolic models, then refinement is verified between concrete parameterized systems. Then, we can take advantage of the property (safety and PLTL properties) preservation by refinement for their verification.
本文给出了一类参数化系统的精化验证方法。这些系统由任意数量的类似过程组成。在(Abdulla et al.， 1999)中，我们用常规语言表示状态，用常规语言上的换能器表示转换。如果我们可以通过动作的加速来计算符号模型，那么我们也可以验证符号模型之间的细化关系R。在一定条件下，如果在两个符号模型之间验证R，则在具体参数化系统之间验证细化。然后，我们可以利用属性(安全和PLTL属性)保存的优势，通过细化来进行验证。
{"title":"How to compute the refinement relation for parameterized systems","authors":"F. Bellegarde, C. Charlet, O. Kouchnarenko","doi":"10.1109/MEMCOD.2003.1210095","DOIUrl":"https://doi.org/10.1109/MEMCOD.2003.1210095","url":null,"abstract":"In this paper, we present a refinement verification for a class of parameterized systems. These systems are composed of an arbitrary number of similar processes. As in (Abdulla et al., 199) we represent the states by regular languages and the transitions by transducers over regular languages. If we can compute a symbolic model by acceleration of the actions, then we can also verify a refinement relation R between the symbolic models. We show that, under some conditions, if R is verified between two symbolic models, then refinement is verified between concrete parameterized systems. Then, we can take advantage of the property (safety and PLTL properties) preservation by refinement for their verification.","PeriodicalId":213762,"journal":{"name":"First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134215952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-24DOI: 10.1109/MEMCOD.2003.1210087
Margot Bittner, F. Kammüller
We present an extension of the development method Fusion/ UML that translates the results of analysis and design into the formal specification language Object-Z. The extended process establishes a consistency relationship between analysis and design. Furthermore, a formal specification for the implementation is produced.
{"title":"Translating Fusion/UML to Object-Z","authors":"Margot Bittner, F. Kammüller","doi":"10.1109/MEMCOD.2003.1210087","DOIUrl":"https://doi.org/10.1109/MEMCOD.2003.1210087","url":null,"abstract":"We present an extension of the development method Fusion/ UML that translates the results of analysis and design into the formal specification language Object-Z. The extended process establishes a consistency relationship between analysis and design. Furthermore, a formal specification for the implementation is produced.","PeriodicalId":213762,"journal":{"name":"First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127123893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-24DOI: 10.1007/978-1-4020-8052-4_5
J. Romberg, O. Slotosch, G. Hahn
{"title":"MoDe: a method for system-level architecture evaluation","authors":"J. Romberg, O. Slotosch, G. Hahn","doi":"10.1007/978-1-4020-8052-4_5","DOIUrl":"https://doi.org/10.1007/978-1-4020-8052-4_5","url":null,"abstract":"","PeriodicalId":213762,"journal":{"name":"First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127300886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-24DOI: 10.1109/MEMCOD.2003.1210096
T. Omnés, Gerard Postuma, Jos Verhaegh, M. Boonen, Nick Gatherer
Keeping up with the increase in system design complexity requires the deployment of extensive engineering re-use technologies, so-called platform-based design techniques (Chang et al., 1999). When creating derivatives of such a complex systems-on-chip (SOC) platform, verification represents 70% of the overall cost. In this process, functional verification has become a huge obstacle. Engineers are assumed to know how to ensure conformance to an ambiguous specification by developing a million test vectors, which may represent only 50 milliseconds of real-time operation underlines Bob Payne, CTO Philips Semiconductors US (Scott et al., 2001). Moreover, software is playing an increasing if not dominant role especially in this platform derivative game, resulting in a burning need for a software and hardware functional co-verification solution at the integrated SOC level but also in the early intellectual property (IP) development cycles. In this paper we illustrate the use of SSDE for USB2.0 conformance co-verification.
为了跟上系统设计复杂性的增加，需要部署广泛的工程重用技术，即所谓的基于平台的设计技术(Chang et al.， 1999)。当创建这种复杂的片上系统(SOC)平台的衍生产品时，验证占总成本的70%。在此过程中，功能验证成为一个巨大的障碍。工程师被认为知道如何通过开发一百万个测试向量来确保符合模糊的规范，这可能只代表50毫秒的实时操作，飞利浦半导体美国首席技术官Bob Payne强调(Scott等人，2001年)。此外，特别是在这个平台衍生游戏中，软件正在发挥越来越重要的作用，导致在集成SOC级别以及早期知识产权(IP)开发周期中对软件和硬件功能协同验证解决方案的迫切需求。在本文中，我们演示了使用SSDE进行USB2.0一致性协同验证。
{"title":"Using SSDE for USB2.0 conformance co-verification","authors":"T. Omnés, Gerard Postuma, Jos Verhaegh, M. Boonen, Nick Gatherer","doi":"10.1109/MEMCOD.2003.1210096","DOIUrl":"https://doi.org/10.1109/MEMCOD.2003.1210096","url":null,"abstract":"Keeping up with the increase in system design complexity requires the deployment of extensive engineering re-use technologies, so-called platform-based design techniques (Chang et al., 1999). When creating derivatives of such a complex systems-on-chip (SOC) platform, verification represents 70% of the overall cost. In this process, functional verification has become a huge obstacle. Engineers are assumed to know how to ensure conformance to an ambiguous specification by developing a million test vectors, which may represent only 50 milliseconds of real-time operation underlines Bob Payne, CTO Philips Semiconductors US (Scott et al., 2001). Moreover, software is playing an increasing if not dominant role especially in this platform derivative game, resulting in a burning need for a software and hardware functional co-verification solution at the integrated SOC level but also in the early intellectual property (IP) development cycles. In this paper we illustrate the use of SSDE for USB2.0 conformance co-verification.","PeriodicalId":213762,"journal":{"name":"First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125226891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-24DOI: 10.1109/MEMCOD.2003.1210107
D. Potop-Butucaru, R. Simone
Several efficient compilation techniques have been recently proposed for the generation of sequential (C) code from Esterel programs. Consisting essentially in direct simulation of the reactive features of the language, these techniques need now to be accommodated with traditional issues of Esterel - the definition of formal semantics, the constructive causality, and the design of efficient and correct methods for analysis and optimization. We address some of these problems by defining a new intermediate model for the representation of Esterel programs. The new representation level preserves much of the initial program structure while making the control flow pattern and the hierarchical state structure explicit. It supports the full Esterel semantics, and it is a good support for efficient analysis, optimization, and code generation algorithms based on static analysis.
{"title":"Optimizations for faster execution of Esterel programs","authors":"D. Potop-Butucaru, R. Simone","doi":"10.1109/MEMCOD.2003.1210107","DOIUrl":"https://doi.org/10.1109/MEMCOD.2003.1210107","url":null,"abstract":"Several efficient compilation techniques have been recently proposed for the generation of sequential (C) code from Esterel programs. Consisting essentially in direct simulation of the reactive features of the language, these techniques need now to be accommodated with traditional issues of Esterel - the definition of formal semantics, the constructive causality, and the design of efficient and correct methods for analysis and optimization. We address some of these problems by defining a new intermediate model for the representation of Esterel programs. The new representation level preserves much of the initial program structure while making the control flow pattern and the hierarchical state structure explicit. It supports the full Esterel semantics, and it is a good support for efficient analysis, optimization, and code generation algorithms based on static analysis.","PeriodicalId":213762,"journal":{"name":"First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130303825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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