A new approach for the translation of SDL specifications to a mixed hardware/software system is presented. Based on the computational model of communicating extended finite state machines (EFSM) the control flow is separated from data flow of the SDL process. Hence for the first time it is possible to generate a mixed hardware/software implementation of an SDL process. This technique also reduces the complexity for high-level and register-transfer synthesis tools for the hardware parts of the system. The advantage of this methodology is shown by a design example of a wireless communication chip.
{"title":"Generating mixing hardware/software systems from SDL specifications","authors":"F. Slomka, Matthias Dörfel, Ralf Münzenberger","doi":"10.1145/371636.371699","DOIUrl":"https://doi.org/10.1145/371636.371699","url":null,"abstract":"A new approach for the translation of SDL specifications to a mixed hardware/software system is presented. Based on the computational model of communicating extended finite state machines (EFSM) the control flow is separated from data flow of the SDL process. Hence for the first time it is possible to generate a mixed hardware/software implementation of an SDL process. This technique also reduces the complexity for high-level and register-transfer synthesis tools for the hardware parts of the system. The advantage of this methodology is shown by a design example of a wireless communication chip.","PeriodicalId":220509,"journal":{"name":"International Symposium on Hardware/Software Codesign","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127599845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we address the problem of minimizing buffer storage requirement in buffer binding for SDF (Synchronous Dataflow) graphs. First, we propose a new two-port FIFO buffer structure that can be efficiently shared by two producer/consumer pairs. Then we propose a buffer binding algorithm based on this two-port buffer structure for minimizing the buffer size requirement. Experimental results demonstrate 9.8%~37.8% improvement in buffer requirement compared to the conventional approaches.
{"title":"Area-efficient buffer binding based on a novel two-port FIFO structure","authors":"Kyoungseok Rha, Kiyoung Choi","doi":"10.1145/371636.371700","DOIUrl":"https://doi.org/10.1145/371636.371700","url":null,"abstract":"In this paper, we address the problem of minimizing buffer storage requirement in buffer binding for SDF (Synchronous Dataflow) graphs. First, we propose a new two-port FIFO buffer structure that can be efficiently shared by two producer/consumer pairs. Then we propose a buffer binding algorithm based on this two-port buffer structure for minimizing the buffer size requirement. Experimental results demonstrate 9.8%~37.8% improvement in buffer requirement compared to the conventional approaches.","PeriodicalId":220509,"journal":{"name":"International Symposium on Hardware/Software Codesign","volume":"33 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131776042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Embedded computing systems have, of course, been around since the 1970’s and the introduction of the microprocessor. These earliest embedded systems required hand-crafting because resources were so tight. However, even in the 1980’s, high-performance processors were available for embedded applications. These high-performance processors were powerful enough to ignite interest in more automated design methods.
{"title":"CODES and co-design: a look back and a look forward","authors":"W. Wolf","doi":"10.1145/371636.371645","DOIUrl":"https://doi.org/10.1145/371636.371645","url":null,"abstract":"Embedded computing systems have, of course, been around since the 1970’s and the introduction of the microprocessor. These earliest embedded systems required hand-crafting because resources were so tight. However, even in the 1980’s, high-performance processors were available for embedded applications. These high-performance processors were powerful enough to ignite interest in more automated design methods.","PeriodicalId":220509,"journal":{"name":"International Symposium on Hardware/Software Codesign","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129730651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Brunel, E. Kock, W. Kruijtzer, H. Kenter, W. Smits
Two levels of interfaces are introduced for modules of intellectual property that can be used to create a video system on chip. Application-level transactions are used for programming the functionality of the system. They are refined into system transactions when mapping to the architecture model that underpins our approach. This supports the definition of IPs that target software and/or hardware implementation and can be hooked to "any" bus through the virtual component interface of the VSI Alliance. We implement this approach, including a model for assessing the performance of system transactions, in a system design methodology that is refined in the ESPRIT/OMI COSY project.
{"title":"Communication refinement in video systems on chip","authors":"J. Brunel, E. Kock, W. Kruijtzer, H. Kenter, W. Smits","doi":"10.1145/301177.301511","DOIUrl":"https://doi.org/10.1145/301177.301511","url":null,"abstract":"Two levels of interfaces are introduced for modules of intellectual property that can be used to create a video system on chip. Application-level transactions are used for programming the functionality of the system. They are refined into system transactions when mapping to the architecture model that underpins our approach. This supports the definition of IPs that target software and/or hardware implementation and can be hooked to \"any\" bus through the virtual component interface of the VSI Alliance. We implement this approach, including a model for assessing the performance of system transactions, in a system design methodology that is refined in the ESPRIT/OMI COSY project.","PeriodicalId":220509,"journal":{"name":"International Symposium on Hardware/Software Codesign","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131103401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Genoe, C. Lennard, J. Kunkel, B. Bailey, G. D. Jong, G. Martin, M. Hashmi, Shay Ben-Chorin, A. Haverinen
Reuse of Intellectual Property (IP), or Virtual Components (VCs), from different internal and external sources in Systems-on-Chip, allows companies to focus the R&D to their own core competencies, and to effectively use other companies' specialized expertise for other parts. Such a model can only work if there the microelectronics system industry worldwide can establish an unified vision with a set of open technical standards. This view is quite similar to design practices at the board level today. However, the complexities of future systems-on-chips will largely exceed the ones that we currently know at a board. Moreover, prototypes require costly silicon runs, less signals are visible for probing, less debugging facilities are available, and it will be much more difficult to analyze possible problems when combining several components. Therefore, these virtual components need specific models, to analyse, compare, debug and validate complete system chips and all their interfaces before processing the real silicon, but already starting in the early design phases. This is what is meant today with 'Virtual Prototyping'.
{"title":"How standards will enable hardware/software co-design","authors":"M. Genoe, C. Lennard, J. Kunkel, B. Bailey, G. D. Jong, G. Martin, M. Hashmi, Shay Ben-Chorin, A. Haverinen","doi":"10.1145/301177.301535","DOIUrl":"https://doi.org/10.1145/301177.301535","url":null,"abstract":"Reuse of Intellectual Property (IP), or Virtual Components (VCs), from different internal and external sources in Systems-on-Chip, allows companies to focus the R&D to their own core competencies, and to effectively use other companies' specialized expertise for other parts. Such a model can only work if there the microelectronics system industry worldwide can establish an unified vision with a set of open technical standards. This view is quite similar to design practices at the board level today. However, the complexities of future systems-on-chips will largely exceed the ones that we currently know at a board. Moreover, prototypes require costly silicon runs, less signals are visible for probing, less debugging facilities are available, and it will be much more difficult to analyze possible problems when combining several components. Therefore, these virtual components need specific models, to analyse, compare, debug and validate complete system chips and all their interfaces before processing the real silicon, but already starting in the early design phases. This is what is meant today with 'Virtual Prototyping'.","PeriodicalId":220509,"journal":{"name":"International Symposium on Hardware/Software Codesign","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117153444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Kienhuis, E. Deprettere, K. Vissers, P. V. D. Wolf
Systems in the domain of high-performance video signal processing are becoming more and more programmable. We suggest an approach to design such systems that involves measuring, via simulation, the performance of various architectures on which a set of applications are mapped. This approach requires a retargetable simulator for an architecture template. We describe the retargetable simulator that we constructed for a stream-oriented application-specific dataflow architecture. For each architecture instance of the architecture template, a specific simulator is derived in three steps: the architecture instance is constructed, an execution model is added, and the executable architecture is instrumented to obtain performance numbers. We used object oriented principles together with a high-level simulation mechanism to ensure retargetability and an efficient simulation speed. Finally we explain how a retargetable simulator can be encapsulated within an environment for automated design space exploration.
{"title":"The construction of a retargetable simulator for an architecture template","authors":"B. Kienhuis, E. Deprettere, K. Vissers, P. V. D. Wolf","doi":"10.1109/HSC.1998.666249","DOIUrl":"https://doi.org/10.1109/HSC.1998.666249","url":null,"abstract":"Systems in the domain of high-performance video signal processing are becoming more and more programmable. We suggest an approach to design such systems that involves measuring, via simulation, the performance of various architectures on which a set of applications are mapped. This approach requires a retargetable simulator for an architecture template. We describe the retargetable simulator that we constructed for a stream-oriented application-specific dataflow architecture. For each architecture instance of the architecture template, a specific simulator is derived in three steps: the architecture instance is constructed, an execution model is added, and the executable architecture is instrumented to obtain performance numbers. We used object oriented principles together with a high-level simulation mechanism to ensure retargetability and an efficient simulation speed. Finally we explain how a retargetable simulator can be encapsulated within an environment for automated design space exploration.","PeriodicalId":220509,"journal":{"name":"International Symposium on Hardware/Software Codesign","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117275276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Balarin, M. Chiodo, Attila Jurecska, L. Lavagno, B. Tabbara, A. Sangiovanni-Vincentelli
Embedded systems are typically implemented as a set of communicating components some of which are implemented in hardware and some of which are implemented in software. Usually many software components share a processor. A real-time operating system (RTOS) is used to enable sharing and provide a communication mechanism between components. Commercial RTOSs are available for many popular micro-controllers. Using them provides significant reduction in design time and often leads to better structured and more maintainable systems. However, since they have to be quite general, they are not efficient enough for many applications, either in memory usage or in run times. Thus, it is often the case that RTOSs are hand coded by an expert for a particular application. This approach is obviously slow, expensive and error-prone.In this paper we propose an alternative where a RTOS is automatically generated based on a high-level description of the system. RTOSs created in our approach offer an ease of use comparable to commercial RTOSs, and yet since they are generated for a specific example, they can be optimized based on the same information used to optimize hand-written code. We have implemented our approach within POLIS, a system for HW/SW co-design of embedded system. To evaluate the POLIS-generated RTOS we have developed a prototyping environment which we use to compare POLIS against a commercial operating system.
{"title":"Automatic Generation of a Real-Time Operating System for Embedded Systems","authors":"F. Balarin, M. Chiodo, Attila Jurecska, L. Lavagno, B. Tabbara, A. Sangiovanni-Vincentelli","doi":"10.1145/792768.793505","DOIUrl":"https://doi.org/10.1145/792768.793505","url":null,"abstract":"Embedded systems are typically implemented as a set of communicating components some of which are implemented in hardware and some of which are implemented in software. Usually many software components share a processor. A real-time operating system (RTOS) is used to enable sharing and provide a communication mechanism between components. Commercial RTOSs are available for many popular micro-controllers. Using them provides significant reduction in design time and often leads to better structured and more maintainable systems. However, since they have to be quite general, they are not efficient enough for many applications, either in memory usage or in run times. Thus, it is often the case that RTOSs are hand coded by an expert for a particular application. This approach is obviously slow, expensive and error-prone.In this paper we propose an alternative where a RTOS is automatically generated based on a high-level description of the system. RTOSs created in our approach offer an ease of use comparable to commercial RTOSs, and yet since they are generated for a specific example, they can be optimized based on the same information used to optimize hand-written code. We have implemented our approach within POLIS, a system for HW/SW co-design of embedded system. To evaluate the POLIS-generated RTOS we have developed a prototyping environment which we use to compare POLIS against a commercial operating system.","PeriodicalId":220509,"journal":{"name":"International Symposium on Hardware/Software Codesign","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115062365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A well -known challenge during processor design is to obtain the best possible results for a typical target application domain that is generally described as a set of benchmarks. Obtaining the best possible result in turn becomes a complex tradeoff between the generality of the processor and the physical characteristics. A custom instruction to perform a task can result in significant improvements for an application, but generally, at the expense of some overhead for all other applications. In the recent years, Application-Specific Instruction-Set Processors (ASIP) have gained popularity in production chips as well as in the research community. In this paper, we present a unique architecture and methodology to design ASIPs in the embedded controller domain by customizing an existing processor instruction set and architecture rather than creating an entirely new ASIP tuned to a benchmark.
{"title":"An ASIP design methodology for embedded systems","authors":"Kayhan Küçükçakar","doi":"10.1145/301177.301190","DOIUrl":"https://doi.org/10.1145/301177.301190","url":null,"abstract":"A well -known challenge during processor design is to obtain the best possible results for a typical target application domain that is generally described as a set of benchmarks. Obtaining the best possible result in turn becomes a complex tradeoff between the generality of the processor and the physical characteristics. A custom instruction to perform a task can result in significant improvements for an application, but generally, at the expense of some overhead for all other applications. In the recent years, Application-Specific Instruction-Set Processors (ASIP) have gained popularity in production chips as well as in the research community. In this paper, we present a unique architecture and methodology to design ASIPs in the embedded controller domain by customizing an existing processor instruction set and architecture rather than creating an entirely new ASIP tuned to a benchmark.","PeriodicalId":220509,"journal":{"name":"International Symposium on Hardware/Software Codesign","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127511719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：