Pub Date : 2020-10-01DOI: 10.1109/ISCAS45731.2020.9180435
Minho Kwon, Seung-hyun Lim, Hyeokjong Lee, Il-Seon Ha, Moo-Young Kim, Il-Jin Seo, Suho Lee, Yongsuk Choi, Kyunghoon Kim, Hansoo Lee, Won-Woong Kim, Seonghye Park, K. Koh, Jesuk Lee, Yongin Park
This paper presents a low-power stacked CMOS image sensor (CIS) in 65/14nm process. With 14nm process, we could achieve 29% less power consumption than the conventional CIS in 65/28nm process. The measured random telegraph noise (RTN) result shows the 65/14nm stacked CIS to guarantee the commercial sensor image quality even though a fin field-effect transistor (FinFET) process is three-dimension channel structure. The pixel array of the implemented chip consists of 12-mega pixels (Mp) with a dual-photodiode (2PD) in 1.4μm pixel pitch, and the sensor output provides 120 frames per second while it consumes 612mW for 12Mp image and 3Mp auto-focus data via a mobile industry processor interface (MIPI) physical layer (DPHY) up to 6.5Gbps/lane. The measured random noise is 2.2e-at 16× analog gain, and figure-of-merit (FoM) of analog-to-digital converters (ADCs) achieves 0.46e-nJ.
{"title":"A Low-Power 65/14nm Stacked CMOS Image Sensor","authors":"Minho Kwon, Seung-hyun Lim, Hyeokjong Lee, Il-Seon Ha, Moo-Young Kim, Il-Jin Seo, Suho Lee, Yongsuk Choi, Kyunghoon Kim, Hansoo Lee, Won-Woong Kim, Seonghye Park, K. Koh, Jesuk Lee, Yongin Park","doi":"10.1109/ISCAS45731.2020.9180435","DOIUrl":"https://doi.org/10.1109/ISCAS45731.2020.9180435","url":null,"abstract":"This paper presents a low-power stacked CMOS image sensor (CIS) in 65/14nm process. With 14nm process, we could achieve 29% less power consumption than the conventional CIS in 65/28nm process. The measured random telegraph noise (RTN) result shows the 65/14nm stacked CIS to guarantee the commercial sensor image quality even though a fin field-effect transistor (FinFET) process is three-dimension channel structure. The pixel array of the implemented chip consists of 12-mega pixels (Mp) with a dual-photodiode (2PD) in 1.4μm pixel pitch, and the sensor output provides 120 frames per second while it consumes 612mW for 12Mp image and 3Mp auto-focus data via a mobile industry processor interface (MIPI) physical layer (DPHY) up to 6.5Gbps/lane. The measured random noise is 2.2e-at 16× analog gain, and figure-of-merit (FoM) of analog-to-digital converters (ADCs) achieves 0.46e-nJ.","PeriodicalId":232502,"journal":{"name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"427 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115654706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-01DOI: 10.1109/ISCAS45731.2020.9180667
Xiaoyuan Wang, Pengfei Zhou, C. Jin, Guangyi Wang, H. Iu
Memristors have great application in many fields such as neural networks, non-volatile memory and nonlinear circuits by virtue of the nanoscale and non-volatile characteristics. Multi-valued devices possess significant meaning in digital logic circuit, chaos control and synapse networks. In this paper, the concept of multi-valued memristors is proposed, and the ternary flux-controlled memristor is taken as an example investigated concretely. Moreover, the specific ternary mathematical model is given and a series of numerical analyses have been studied. After that, a ternary flux-controlled memristor emulator is realized by off-the-shelf circuit components, both Multisim simulations and hardware experiments are performed to verify its effectiveness and the results shows that the theoretical analysis based on the mathematical model is in good agreement with the simulation and experimental results, which laid the theoretical foundation for the construction of multi-valued digital logic and other multi-valued applications.
{"title":"Mathematic Modeling and Circuit Implementation on Multi-Valued Memristor","authors":"Xiaoyuan Wang, Pengfei Zhou, C. Jin, Guangyi Wang, H. Iu","doi":"10.1109/ISCAS45731.2020.9180667","DOIUrl":"https://doi.org/10.1109/ISCAS45731.2020.9180667","url":null,"abstract":"Memristors have great application in many fields such as neural networks, non-volatile memory and nonlinear circuits by virtue of the nanoscale and non-volatile characteristics. Multi-valued devices possess significant meaning in digital logic circuit, chaos control and synapse networks. In this paper, the concept of multi-valued memristors is proposed, and the ternary flux-controlled memristor is taken as an example investigated concretely. Moreover, the specific ternary mathematical model is given and a series of numerical analyses have been studied. After that, a ternary flux-controlled memristor emulator is realized by off-the-shelf circuit components, both Multisim simulations and hardware experiments are performed to verify its effectiveness and the results shows that the theoretical analysis based on the mathematical model is in good agreement with the simulation and experimental results, which laid the theoretical foundation for the construction of multi-valued digital logic and other multi-valued applications.","PeriodicalId":232502,"journal":{"name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123079216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-01DOI: 10.1109/ISCAS45731.2020.9181264
Yutaro Shimomura, Takuya Shimada, Ryuya Kirihara, T. Kumaki
This paper introduces the development of LED-based stego-panel. While this demonstration system displays dot matrix images through a CMOS image sensor, these informations are imperceptible to human eyes. Thus, this stego-panel can use interior illumination and transmit several messages to specific persons by using smartphone. The goal of this research is to add new values to LED illumination. We are developing prototype of the LED-based stego-panel and can provide new and exciting experiences for many visitors.
{"title":"Live Demonstration: Development of LED-Based Stego-Panel for New Smartphone Usage","authors":"Yutaro Shimomura, Takuya Shimada, Ryuya Kirihara, T. Kumaki","doi":"10.1109/ISCAS45731.2020.9181264","DOIUrl":"https://doi.org/10.1109/ISCAS45731.2020.9181264","url":null,"abstract":"This paper introduces the development of LED-based stego-panel. While this demonstration system displays dot matrix images through a CMOS image sensor, these informations are imperceptible to human eyes. Thus, this stego-panel can use interior illumination and transmit several messages to specific persons by using smartphone. The goal of this research is to add new values to LED illumination. We are developing prototype of the LED-based stego-panel and can provide new and exciting experiences for many visitors.","PeriodicalId":232502,"journal":{"name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123170912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a fast transient low-dropout regulator (LDO) with bulk modulation technique and dynamic transient boost circuit (TBC) for system-on-chip (SoC) applications. The conventional bulk modulation and dynamic biasing techniques failed to obtain low quiescent current and better stability at no-load conditions. The proposed bulk modulation technique implemented by using only one error amplifier with two different gain stages to achieve the small quiescent current and to obtain good regulation with better driving capability. The proposed TBC combines the dynamic biasing and output compensation techniques to enhance the transient response of LDO drastically. The proposed design is simulated in the 40nm LVT CMOS process shows that the LDO delivers 1V output voltage and consumes 15μA of quiescent current with the supply voltage of 1.1V. When the load current changes from 100nA to 10mA with a large slew rate of 200ps, undershoot and settling time are 450mV and 8ns respectively. Compared to LDO without TBC, the proposed LDO offers good stability, better driving capability, ∼10× less undershoot and ∼10× fast settling time.
{"title":"A 8-ns Settling Time Fully Integrated LDO with Dynamic Biasing and Bulk Modulation Techniques in 40nm CMOS","authors":"T. Nagateja, Neha Kumari, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai","doi":"10.1109/ISCAS45731.2020.9181197","DOIUrl":"https://doi.org/10.1109/ISCAS45731.2020.9181197","url":null,"abstract":"This paper presents a fast transient low-dropout regulator (LDO) with bulk modulation technique and dynamic transient boost circuit (TBC) for system-on-chip (SoC) applications. The conventional bulk modulation and dynamic biasing techniques failed to obtain low quiescent current and better stability at no-load conditions. The proposed bulk modulation technique implemented by using only one error amplifier with two different gain stages to achieve the small quiescent current and to obtain good regulation with better driving capability. The proposed TBC combines the dynamic biasing and output compensation techniques to enhance the transient response of LDO drastically. The proposed design is simulated in the 40nm LVT CMOS process shows that the LDO delivers 1V output voltage and consumes 15μA of quiescent current with the supply voltage of 1.1V. When the load current changes from 100nA to 10mA with a large slew rate of 200ps, undershoot and settling time are 450mV and 8ns respectively. Compared to LDO without TBC, the proposed LDO offers good stability, better driving capability, ∼10× less undershoot and ∼10× fast settling time.","PeriodicalId":232502,"journal":{"name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116690942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-01DOI: 10.1109/ISCAS45731.2020.9180410
M. Shiozaki, Y. Hori, Tatsuya Oyama, M. Shirahata, T. Fujino
The use of physically unclonable functions (PUFs) as a new cryptographic technique is gaining attention. Challenge-response authentication and key generation (key storage) are well known as major applications using PUFs. When PUFs are applied to these applications, min-entropy estimation is essential. The min-entropy is a measure of the lower bound of the unpredictability of PUF responses. Many studies have estimated the min-entropy of PUFs, and several of these studies dealt with PUFs with independent and identically distributed (IID) PUF responses. Few studies have focused on non-IID PUFs. One reason is that some causes of entropy loss are complicatedly intertwined, and the entropy estimation of non-IID PUFs is hard. Thus, it is first necessary to break down the intertwined causes to estimate min-entropy. In this paper, we present typical causes of entropy loss during PUF implementation and propose a cause analysis method using the Inter-Hamming distance (HD), which is one of major performance metrics of PUFs. And the proposed method was applied to prototyped PUFs designed with a 180-nm CMOS process. We demonstrate that the causes of entropy loss on each PUF can be broken down according to the analysis results.
{"title":"Cause Analysis Method of Entropy Loss in Physically Unclonable Functions","authors":"M. Shiozaki, Y. Hori, Tatsuya Oyama, M. Shirahata, T. Fujino","doi":"10.1109/ISCAS45731.2020.9180410","DOIUrl":"https://doi.org/10.1109/ISCAS45731.2020.9180410","url":null,"abstract":"The use of physically unclonable functions (PUFs) as a new cryptographic technique is gaining attention. Challenge-response authentication and key generation (key storage) are well known as major applications using PUFs. When PUFs are applied to these applications, min-entropy estimation is essential. The min-entropy is a measure of the lower bound of the unpredictability of PUF responses. Many studies have estimated the min-entropy of PUFs, and several of these studies dealt with PUFs with independent and identically distributed (IID) PUF responses. Few studies have focused on non-IID PUFs. One reason is that some causes of entropy loss are complicatedly intertwined, and the entropy estimation of non-IID PUFs is hard. Thus, it is first necessary to break down the intertwined causes to estimate min-entropy. In this paper, we present typical causes of entropy loss during PUF implementation and propose a cause analysis method using the Inter-Hamming distance (HD), which is one of major performance metrics of PUFs. And the proposed method was applied to prototyped PUFs designed with a 180-nm CMOS process. We demonstrate that the causes of entropy loss on each PUF can be broken down according to the analysis results.","PeriodicalId":232502,"journal":{"name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117059686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-01DOI: 10.1109/ISCAS45731.2020.9180924
Shamma Nasrin, S. Ramakrishna, Theja Tulabandhula, A. Trivedi
In this work, we introduce bitcell array-based support parameters to improve the prediction accuracy of SRAM-based binarized neural network (SRAM-BNN). Our approach enhances the training weight space of SRAM-BNN while requiring minimal overheads to a typical design. More flexibility of the weight space leads to higher prediction accuracy in our design. We adapt row digital-to-analog (DAC) converter, and computing flow in SRAM-BNN for bitcell array-based weight supports. Using the discussed interventions, our scheme also allows a dynamic trade-off of accuracy against energy to address dynamic energy constraints in typical real-time applications. Our approach reduces classification error in MNIST from 1.4% to 0.91%. To reduce the power overheads, we propose a dynamic drop out of support parameters, which also reduces the processing energy of the in-SRAM weight-input product Our architecture can dropout 52% of the bitcell array-based support parameters with only minimal accuracy degradation. We also characterize our design under varying degrees of process variability in the transistors.
{"title":"Supported-BinaryNet: Bitcell Array-Based Weight Supports for Dynamic Accuracy-Energy Trade-Offs in SRAM-Based Binarized Neural Network","authors":"Shamma Nasrin, S. Ramakrishna, Theja Tulabandhula, A. Trivedi","doi":"10.1109/ISCAS45731.2020.9180924","DOIUrl":"https://doi.org/10.1109/ISCAS45731.2020.9180924","url":null,"abstract":"In this work, we introduce bitcell array-based support parameters to improve the prediction accuracy of SRAM-based binarized neural network (SRAM-BNN). Our approach enhances the training weight space of SRAM-BNN while requiring minimal overheads to a typical design. More flexibility of the weight space leads to higher prediction accuracy in our design. We adapt row digital-to-analog (DAC) converter, and computing flow in SRAM-BNN for bitcell array-based weight supports. Using the discussed interventions, our scheme also allows a dynamic trade-off of accuracy against energy to address dynamic energy constraints in typical real-time applications. Our approach reduces classification error in MNIST from 1.4% to 0.91%. To reduce the power overheads, we propose a dynamic drop out of support parameters, which also reduces the processing energy of the in-SRAM weight-input product Our architecture can dropout 52% of the bitcell array-based support parameters with only minimal accuracy degradation. We also characterize our design under varying degrees of process variability in the transistors.","PeriodicalId":232502,"journal":{"name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"133 2-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121344025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-01DOI: 10.1109/ISCAS45731.2020.9181039
You-Shin Chen, Tzu-Hsiang Hsu, Guan-Cheng Chen, Chien-Wen Chen, C. Hsieh
This paper presents a monolithic optical encoder using CMOS image sensor (CIS) with background light cancellation. Both the absolute and incremental encoders are designed and fabricated on the same chip with dual photodiode arrays and the corresponding readout circuits. The absolute encoder is implemented using 42 columns of pixel with adjustable dual-threshold quantizer. The incremental encoder is implemented using the developed common-centroid interlacing (CCI) photodiode (PD) arrangement for the sensing of four quadrature sinusoidal signal with a 90° phase shift to each other. A fully-differential transimpedance amplifier (FDTIA) with current-mode subtraction (CMS) is proposed to achieve the common-mode signal rejection and background light cancellation. With the implemented CCI PD array, CMS FDTIA, programmable gain amplifiers (PGA), and 12-b SAR ADCs, the prototype achieves a SNR of 60dB, a total power of 10mW, and the maximum displacement error of 0.22μm. Compared to the reported work [5], it achieves a SNR improvement of 15dB, a 2× power reduction, and a 2× accuracy.
本文提出了一种采用背景光对消的CMOS图像传感器的单片光学编码器。采用双光电二极管阵列和相应的读出电路，在同一芯片上设计制作了绝对编码器和增量编码器。绝对编码器采用42列像素和可调双阈值量化器实现。增量编码器采用所开发的共质心隔行(CCI)光电二极管(PD)装置实现，用于检测四个相互相移90°的正交正弦信号。提出了一种采用电流模减法的全差分跨阻放大器(FDTIA)来实现共模信号抑制和背景光消除。该样机采用CCI PD阵列、CMS FDTIA、可编程增益放大器(PGA)和12b SAR adc，信噪比为60dB，总功率为10mW，最大位移误差为0.22μm。与报道的工作[5]相比，它实现了15dB的信噪比提高，功耗降低2倍，精度提高2倍。
{"title":"A Monolithic Optical Encoder using CMOS Image Sensor with Background Light Cancellation","authors":"You-Shin Chen, Tzu-Hsiang Hsu, Guan-Cheng Chen, Chien-Wen Chen, C. Hsieh","doi":"10.1109/ISCAS45731.2020.9181039","DOIUrl":"https://doi.org/10.1109/ISCAS45731.2020.9181039","url":null,"abstract":"This paper presents a monolithic optical encoder using CMOS image sensor (CIS) with background light cancellation. Both the absolute and incremental encoders are designed and fabricated on the same chip with dual photodiode arrays and the corresponding readout circuits. The absolute encoder is implemented using 42 columns of pixel with adjustable dual-threshold quantizer. The incremental encoder is implemented using the developed common-centroid interlacing (CCI) photodiode (PD) arrangement for the sensing of four quadrature sinusoidal signal with a 90° phase shift to each other. A fully-differential transimpedance amplifier (FDTIA) with current-mode subtraction (CMS) is proposed to achieve the common-mode signal rejection and background light cancellation. With the implemented CCI PD array, CMS FDTIA, programmable gain amplifiers (PGA), and 12-b SAR ADCs, the prototype achieves a SNR of 60dB, a total power of 10mW, and the maximum displacement error of 0.22μm. Compared to the reported work [5], it achieves a SNR improvement of 15dB, a 2× power reduction, and a 2× accuracy.","PeriodicalId":232502,"journal":{"name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127117577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-01DOI: 10.1109/ISCAS45731.2020.9181012
Jusung Kim, Junning Jiang, J. Silva-Martínez, A. Karsilayan
A highly-linear I-channel receiver prototype is presented for a 3 to 6 GHz broadband radio system with a 200 MHz baseband bandwidth and verified to operate under congested spectrum environments. A direct conversion receiver developed from this prototype is suitable for a cognitive radio, fifth-generation (5G) receiver, and other wireless systems with a total (in-band signal plus blocker) power above −6.0 dBm. The broadband receiver consists of a low-noise transconductance amplifier, a passive mixer, a wideband transimpedance amplifier and a power-efficient minimally-invasive baseband filter. The low-noise transconductance amplifier with high linearity employs a cross-coupled structure and resistive degeneration to achieve low noise and high linearity simultaneously. The common-gate based LNTA achieves 2.3 dB noise figure in simulation. Fabricated in a mainstream 40 nm CMOS technology, the worst-case measured system noise figure is under 5.8 dB at 3 MHz baseband frequency, and the conversion gain is larger than 12.8 dB with passband variations under 2 dB from 1 MHz up to 200 MHz signal bandwidth. Over 3 to 6 GHz, the receiver's in-band IIP3 and input P1db are higher than 15.1 dBm and 3.0 dBm, respectively, whereas the power consumption varies from 64.1 mW to 69.6 mW.
{"title":"A 3 to 6 GHz Highly Linear I-Channel Receiver with over +3.0 dBm In-Band P1dB and 200 MHz Baseband Bandwidth Suitable for 5G Wireless and Cognitive Radio Applications","authors":"Jusung Kim, Junning Jiang, J. Silva-Martínez, A. Karsilayan","doi":"10.1109/ISCAS45731.2020.9181012","DOIUrl":"https://doi.org/10.1109/ISCAS45731.2020.9181012","url":null,"abstract":"A highly-linear I-channel receiver prototype is presented for a 3 to 6 GHz broadband radio system with a 200 MHz baseband bandwidth and verified to operate under congested spectrum environments. A direct conversion receiver developed from this prototype is suitable for a cognitive radio, fifth-generation (5G) receiver, and other wireless systems with a total (in-band signal plus blocker) power above −6.0 dBm. The broadband receiver consists of a low-noise transconductance amplifier, a passive mixer, a wideband transimpedance amplifier and a power-efficient minimally-invasive baseband filter. The low-noise transconductance amplifier with high linearity employs a cross-coupled structure and resistive degeneration to achieve low noise and high linearity simultaneously. The common-gate based LNTA achieves 2.3 dB noise figure in simulation. Fabricated in a mainstream 40 nm CMOS technology, the worst-case measured system noise figure is under 5.8 dB at 3 MHz baseband frequency, and the conversion gain is larger than 12.8 dB with passband variations under 2 dB from 1 MHz up to 200 MHz signal bandwidth. Over 3 to 6 GHz, the receiver's in-band IIP3 and input P1db are higher than 15.1 dBm and 3.0 dBm, respectively, whereas the power consumption varies from 64.1 mW to 69.6 mW.","PeriodicalId":232502,"journal":{"name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127184608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-01DOI: 10.1109/ISCAS45731.2020.9180447
Shidong Zhai, W. Zheng
In this paper, the problem of unanimity of coupled nonlinear systems over coopetition networks is addressed. Specifically, it is investigated whether all system states of coupled nonlinear systems can reach an identical sign after a threshold of time has passed by, which is known as the unanimity. The switched nonlinear systems are considered in the case of coexistence of cooperative and competitive interactions between coupled nonlinear systems. Some conditions that ensure the unanimity of coupled nonlinear systems are derived by exploiting the properties of eventually positive matrices and Lie bracket. The efficiency of the obtained results is validated by an illustrative example.
{"title":"On Unanimity of Nonlinear Systems with Coupling over Coopetition Networks","authors":"Shidong Zhai, W. Zheng","doi":"10.1109/ISCAS45731.2020.9180447","DOIUrl":"https://doi.org/10.1109/ISCAS45731.2020.9180447","url":null,"abstract":"In this paper, the problem of unanimity of coupled nonlinear systems over coopetition networks is addressed. Specifically, it is investigated whether all system states of coupled nonlinear systems can reach an identical sign after a threshold of time has passed by, which is known as the unanimity. The switched nonlinear systems are considered in the case of coexistence of cooperative and competitive interactions between coupled nonlinear systems. Some conditions that ensure the unanimity of coupled nonlinear systems are derived by exploiting the properties of eventually positive matrices and Lie bracket. The efficiency of the obtained results is validated by an illustrative example.","PeriodicalId":232502,"journal":{"name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123319088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-01DOI: 10.1109/ISCAS45731.2020.9181018
Y. Liu, C. Tse, Chunbo Zhu, Siu-Chung Wong
This paper presents a detailed analysis of sensitivity of various second-order and third-order compensated inductive power transfer (IPT) converters, designed for achieving load-independent current (LIC) or load-independent voltage (LIV) output, against input voltage variation. Comparisons of sensitivity for varying input-side inductances are systematically investigated through theoretical circuit analysis and extensive simulation studies. Relationship between second-order and third-order compensation is also explored through the transformation between voltage sources and current sources. The sensitivity analysis provides a convenient guidance for parameter design of IPT systems for achieving the required LIV and LIC operation under wide input range. Besides, the analysis effectively reveals the roles of extra input-side inductors in making the equivalent current source less sensitive, and hence provides a direct and handy interpretation of the choice of higher-order compensation circuits for applications addressing wide ranges of input variations.
{"title":"Comparison of Second-Order and Third-Order Compensation of Inductive Power Transfer Converters Based on Sensitivity Analysis","authors":"Y. Liu, C. Tse, Chunbo Zhu, Siu-Chung Wong","doi":"10.1109/ISCAS45731.2020.9181018","DOIUrl":"https://doi.org/10.1109/ISCAS45731.2020.9181018","url":null,"abstract":"This paper presents a detailed analysis of sensitivity of various second-order and third-order compensated inductive power transfer (IPT) converters, designed for achieving load-independent current (LIC) or load-independent voltage (LIV) output, against input voltage variation. Comparisons of sensitivity for varying input-side inductances are systematically investigated through theoretical circuit analysis and extensive simulation studies. Relationship between second-order and third-order compensation is also explored through the transformation between voltage sources and current sources. The sensitivity analysis provides a convenient guidance for parameter design of IPT systems for achieving the required LIV and LIC operation under wide input range. Besides, the analysis effectively reveals the roles of extra input-side inductors in making the equivalent current source less sensitive, and hence provides a direct and handy interpretation of the choice of higher-order compensation circuits for applications addressing wide ranges of input variations.","PeriodicalId":232502,"journal":{"name":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123548781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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