Bounding the latency of real-time multiprocessor applications is crucial for safety-critical systems. Several approximative analysis approaches exist that can efficiently analyze the latency. However, these approaches produce pessimistic latency results and do not exploit buffer sizing nor exploit additional sequence constraints to reduce the latency. More accurate latency analysis results can be obtained using model checking of timed-automata, however, at the cost of a typically excessive run-time. This paper presents a latency analysis approach for cyclic task graphs using model checking of timed automata of which the run-time is reduced. The approach is applicable for systems in which tasks are executed on shared processors using a Fixed Priority Pre-emptive (FPP) scheduling policy. The reduction in run-time is achieved by pruning the search space of options that need to be analyzed using the model checker by making use of approximative dataflow analysis techniques. The approach exploits dimensioning of buffers to minimize interference and latency. Moreover, sequence constraints are introduced and automatically adapted in order to minimize the latency of the task graph. A WLAN 802.11p transceiver application is used in the case study to compare this hybrid analysis approach to a state-of-the-art approximation based approach that uses iterative buffer sizing. Using our approach, the analyzed latency decreased from 17 μs to 15 μs at the cost of a run-time of 23 minutes instead of a fraction of a second.
{"title":"Hybrid Latency Minimization Approach using Model Checking and Dataflow Analysis","authors":"G. Kuiper, P. Kurtin, M. Bekooij","doi":"10.1145/3078659.3078665","DOIUrl":"https://doi.org/10.1145/3078659.3078665","url":null,"abstract":"Bounding the latency of real-time multiprocessor applications is crucial for safety-critical systems. Several approximative analysis approaches exist that can efficiently analyze the latency. However, these approaches produce pessimistic latency results and do not exploit buffer sizing nor exploit additional sequence constraints to reduce the latency. More accurate latency analysis results can be obtained using model checking of timed-automata, however, at the cost of a typically excessive run-time. This paper presents a latency analysis approach for cyclic task graphs using model checking of timed automata of which the run-time is reduced. The approach is applicable for systems in which tasks are executed on shared processors using a Fixed Priority Pre-emptive (FPP) scheduling policy. The reduction in run-time is achieved by pruning the search space of options that need to be analyzed using the model checker by making use of approximative dataflow analysis techniques. The approach exploits dimensioning of buffers to minimize interference and latency. Moreover, sequence constraints are introduced and automatically adapted in order to minimize the latency of the task graph. A WLAN 802.11p transceiver application is used in the case study to compare this hybrid analysis approach to a state-of-the-art approximation based approach that uses iterative buffer sizing. Using our approach, the analyzed latency decreased from 17 μs to 15 μs at the cost of a run-time of 23 minutes instead of a fraction of a second.","PeriodicalId":240210,"journal":{"name":"Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131171953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Hot Path SSA (HPSSA) form filled a long-standing void by providing an SSA-like intermediate representation that could weave static program code and run-time profile information in a single data structure, thereby facilitating speculative analyses and optimizations. The original algorithm proposed for the Hot Path SSA construction builds HPSSA over non-SSA programs with interleaved SSA and HPSSA construction passes. In this work, we propose a new algorithm for constructing HPSSA programs from programs in the SSA form. Our new algorithm has the following advantages over the original algorithm: firstly, as all modern compilers have built-in SSA construction passes, it is difficult to incorporate the original algorithm within an existing compiler as it requires the compiler writer to intrude in and retrofit the HPSSA construction stages with the SSA construction pass. Our new algorithm can simply be pipelined next to the SSA construction pass with no modification required to existing passes. Secondly, our new algorithm is more efficient than the original algorithm: the original algorithm needs to process all definitions in the program while our new algorithm processes only the φ-functions---a small fraction of all program instructions. Most importantly, our new algorithm is much simpler than the original algorithm. We have implemented our algorithm in the LLVM compiler framework and evaluated its effectiveness by implementing an ILP driven path-profile guided register allocator.
{"title":"Constructing HPSSA over SSA","authors":"Smriti Jaiswal, P. Hegde, Subhajit Roy","doi":"10.1145/3078659.3078660","DOIUrl":"https://doi.org/10.1145/3078659.3078660","url":null,"abstract":"The Hot Path SSA (HPSSA) form filled a long-standing void by providing an SSA-like intermediate representation that could weave static program code and run-time profile information in a single data structure, thereby facilitating speculative analyses and optimizations. The original algorithm proposed for the Hot Path SSA construction builds HPSSA over non-SSA programs with interleaved SSA and HPSSA construction passes. In this work, we propose a new algorithm for constructing HPSSA programs from programs in the SSA form. Our new algorithm has the following advantages over the original algorithm: firstly, as all modern compilers have built-in SSA construction passes, it is difficult to incorporate the original algorithm within an existing compiler as it requires the compiler writer to intrude in and retrofit the HPSSA construction stages with the SSA construction pass. Our new algorithm can simply be pipelined next to the SSA construction pass with no modification required to existing passes. Secondly, our new algorithm is more efficient than the original algorithm: the original algorithm needs to process all definitions in the program while our new algorithm processes only the φ-functions---a small fraction of all program instructions. Most importantly, our new algorithm is much simpler than the original algorithm. We have implemented our algorithm in the LLVM compiler framework and evaluated its effectiveness by implementing an ILP driven path-profile guided register allocator.","PeriodicalId":240210,"journal":{"name":"Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117221541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Juurlink, J. Lucas, Nadjib Mammeri, Martyn Bliss, G. Keramidas, Chrysa Kokkala, A. Richards
The LPGPU2 project is a 30-month-project (Innovation Action) funded by the European Union. Its overall goal is to develop an analysis and visualization framework that enables GPU application developers to improve the performance and power consumption of their applications. To achieve this overall goal, several key objectives need to be achieved. First, several applications (use cases) need to be developed for or ported to low-power GPUs. Thereafter, these applications need to be optimized using the tooling framework. In addition, power measurement devices and power models need to be developed that are 10x more accurate than the state of the art. The project consortium actively promotes open vendor-neutral standards via the Khronos group. This paper briefly reports on the achievements made in the first half of the project, and focuses on the progress made in applications; in power measurement, estimation, and modelling; and in the analysis and visualization tool suite.
{"title":"The LPGPU2 Project: Low-Power Parallel Computing on GPUs: Extended Abstract","authors":"B. Juurlink, J. Lucas, Nadjib Mammeri, Martyn Bliss, G. Keramidas, Chrysa Kokkala, A. Richards","doi":"10.1145/3078659.3078672","DOIUrl":"https://doi.org/10.1145/3078659.3078672","url":null,"abstract":"The LPGPU2 project is a 30-month-project (Innovation Action) funded by the European Union. Its overall goal is to develop an analysis and visualization framework that enables GPU application developers to improve the performance and power consumption of their applications. To achieve this overall goal, several key objectives need to be achieved. First, several applications (use cases) need to be developed for or ported to low-power GPUs. Thereafter, these applications need to be optimized using the tooling framework. In addition, power measurement devices and power models need to be developed that are 10x more accurate than the state of the art. The project consortium actively promotes open vendor-neutral standards via the Khronos group. This paper briefly reports on the achievements made in the first half of the project, and focuses on the progress made in applications; in power measurement, estimation, and modelling; and in the analysis and visualization tool suite.","PeriodicalId":240210,"journal":{"name":"Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125971708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
James Pallister, Steve Kerrison, J. Morse, K. Eder
Safely meeting Worst Case Energy Consumption (WCEC) criteria requires accurate energy modeling of software. We investigate the impact of instruction operand values upon energy consumption in cacheless embedded processors. Existing instruction-level energy models typically use measurements from random input data, providing estimates unsuitable for safe WCEC analysis. We examine probabilistic energy distributions of instructions and propose a model for composing instruction sequences using distributions, enabling WCEC analysis on program basic blocks. The worst case is predicted with statistical analysis. Further, we verify that the energy of embedded benchmarks can be characterised as a distribution, and compare our proposed technique with other methods of estimating energy consumption.
{"title":"Data Dependent Energy Modeling for Worst Case Energy Consumption Analysis","authors":"James Pallister, Steve Kerrison, J. Morse, K. Eder","doi":"10.1145/3078659.3078666","DOIUrl":"https://doi.org/10.1145/3078659.3078666","url":null,"abstract":"Safely meeting Worst Case Energy Consumption (WCEC) criteria requires accurate energy modeling of software. We investigate the impact of instruction operand values upon energy consumption in cacheless embedded processors. Existing instruction-level energy models typically use measurements from random input data, providing estimates unsuitable for safe WCEC analysis. We examine probabilistic energy distributions of instructions and propose a model for composing instruction sequences using distributions, enabling WCEC analysis on program basic blocks. The worst case is predicted with statistical analysis. Further, we verify that the energy of embedded benchmarks can be characterised as a distribution, and compare our proposed technique with other methods of estimating energy consumption.","PeriodicalId":240210,"journal":{"name":"Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122537442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems","authors":"","doi":"10.1145/3078659","DOIUrl":"https://doi.org/10.1145/3078659","url":null,"abstract":"","PeriodicalId":240210,"journal":{"name":"Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133316905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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