Pub Date : 2008-09-22DOI: 10.14236/EWIC/VOCS2008.1
S. Paul, R. Jain, Jianli Pan, M. Bowman
The host centric design of the current Internet does not recognise data and endusers as integral entities of the system. The first generation of Internet has been very successful and yet business, organizations, governments are finding it difficult to enforce their policies on their networks with the same ease that they do other methods of communications and transport. Ad-Hoc solutions e.g. firewalls, NAT, middleboxes etc, that try to mitigate these issues end up providing localized myopic fixes which often hurt the basic underlying principles of the original design. We envision the future internet to be a dynamic, heterogeneous, secure, energy efficient ubiquitous network flexible enough to support innovations and policy enforcements both at the edge and the core. The first step towards the next generation is the redesign of naming and name binding mechanisms. We, therefore, propose a Policy Oriented Network Architecture (PONA) and an abstract two part protocol stack with a virtualization layer in between. We also introduce the concept of generalized communication end-points - hosts, users, data/services, instantiate the ideas with the Mapping and Negotiation layer and provide an integrated framework for the next generation Internet.
{"title":"A Vision of the Next Generation Internet: A Policy Oriented Perspective","authors":"S. Paul, R. Jain, Jianli Pan, M. Bowman","doi":"10.14236/EWIC/VOCS2008.1","DOIUrl":"https://doi.org/10.14236/EWIC/VOCS2008.1","url":null,"abstract":"The host centric design of the current Internet does not recognise data and endusers as integral entities of the system. The first generation of Internet has been very successful and yet business, organizations, governments are finding it difficult to enforce their policies on their networks with the same ease that they do other methods of communications and transport. Ad-Hoc solutions e.g. firewalls, NAT, middleboxes etc, that try to mitigate these issues end up providing localized myopic fixes which often hurt the basic underlying principles of the original design. We envision the future internet to be a dynamic, heterogeneous, secure, energy efficient ubiquitous network flexible enough to support innovations and policy enforcements both at the edge and the core. The first step towards the next generation is the redesign of naming and name binding mechanisms. We, therefore, propose a Policy Oriented Network Architecture (PONA) and an abstract two part protocol stack with a virtualization layer in between. We also introduce the concept of generalized communication end-points - hosts, users, data/services, instantiate the ideas with the Mapping and Negotiation layer and provide an integrated framework for the next generation Internet.","PeriodicalId":247606,"journal":{"name":"BCS International Academic Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131276101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-22DOI: 10.14236/EWIC/VOCS2008.14
Gülay Öke Günel, G. Loukas
In recent years, Denial of Service attacks have evolved into a predominant network security threat. In our previous work, we identified the necessary building blocks for an effective defence mechanism and suggested ways to integrate them. Here, we present the results of this integration on the DoS-resilience of a real networking testbed which runs the Self-Aware CPN routing protocol. The incoming traffic at each node is monitored with a detection mechanism that is based on maximum likelihood estimation. In response to high probability of attack, the traffic is ratelimited proportionally to the measured probability. We illustrate the results of the experiments we have performed to demonstrate the efficiency of the distributed defence system that we propose.
{"title":"Distributed Defence Against Denial of Service Attacks: A Practical View","authors":"Gülay Öke Günel, G. Loukas","doi":"10.14236/EWIC/VOCS2008.14","DOIUrl":"https://doi.org/10.14236/EWIC/VOCS2008.14","url":null,"abstract":"In recent years, Denial of Service attacks have evolved into a predominant network security threat. In our previous work, we identified the necessary building blocks for an effective defence mechanism and suggested ways to integrate them. Here, we present the results of this integration on the DoS-resilience of a real networking testbed which runs the Self-Aware CPN routing protocol. The incoming traffic at each node is monitored with a detection mechanism that is based on maximum likelihood estimation. In response to high probability of attack, the traffic is ratelimited proportionally to the measured probability. We illustrate the results of the experiments we have performed to demonstrate the efficiency of the distributed defence system that we propose.","PeriodicalId":247606,"journal":{"name":"BCS International Academic Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123627487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-22DOI: 10.14236/EWIC/VOCS2008.27
A. Fidjeland, W. Luk, S. Muggleton
This paper describes a customisable processor designed to accelerate execution of inductive logic programming, targeting advanced field-programmable gate array (FPGA) technology. The instruction set and the microarchitecture of the processor are optimised for key operations in logic programming, such as unification and backtracking. Such optimisations reduce external memory access to enable performance comparable to current general-purpose processors, even at much lower clock frequencies. Our processor can be customised to a particular program by excluding unnecessary functional and memory units, and by adapting the size of such units to suit the application. These customisations reduce resource usage while improving performance, and enable accommodating multiple processors on a single FPGA. Such multiprocessor parallelism can be exploited by search-oriented applications in machine learning applications. We find that up to 32 processors can fit on an XC2V6000 FPGA. Using this device, the computational kernel of the machine learning system Progol, when applied to common bioinformatics data sets for learning to identify mutagenesis and protein folds, can yield speedups of up to 15 times over software running on a 2.53GHz Pentium-4 machine. The proposed approach appears promising with the advance of field-programmable technology: the more recent XC4VLX160 device would be capable of supporting up to 65 processors.
{"title":"A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming","authors":"A. Fidjeland, W. Luk, S. Muggleton","doi":"10.14236/EWIC/VOCS2008.27","DOIUrl":"https://doi.org/10.14236/EWIC/VOCS2008.27","url":null,"abstract":"This paper describes a customisable processor designed to accelerate execution of inductive logic programming, targeting advanced field-programmable gate array (FPGA) technology. The instruction set and the microarchitecture of the processor are optimised for key operations in logic programming, such as unification and backtracking. Such optimisations reduce external memory access to enable performance comparable to current general-purpose processors, even at much lower clock frequencies. Our processor can be customised to a particular program by excluding unnecessary functional and memory units, and by adapting the size of such units to suit the application. These customisations reduce resource usage while improving performance, and enable accommodating multiple processors on a single FPGA. Such multiprocessor parallelism can be exploited by search-oriented applications in machine learning applications. We find that up to 32 processors can fit on an XC2V6000 FPGA. Using this device, the computational kernel of the machine learning system Progol, when applied to common bioinformatics data sets for learning to identify mutagenesis and protein folds, can yield speedups of up to 15 times over software running on a 2.53GHz Pentium-4 machine. The proposed approach appears promising with the advance of field-programmable technology: the more recent XC4VLX160 device would be capable of supporting up to 65 processors.","PeriodicalId":247606,"journal":{"name":"BCS International Academic Conference","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121149301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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