Pub Date : 1992-04-01DOI: 10.1109/PCCC.1992.200536
I. Onyuksel
Two different approximate state models are presented for the performance analysis of a shared-memory multiprocessor system. The steady-state solutions for the state transition matrices were obtained by applying an iterative numerical technique. The numerical results illustrate that the state models produce less than 5% approximation error compared to simulation results. It has been observed that the coefficient of variation for the service time of the shared memory has little effect on the system performance.<>
{"title":"Performance modeling of a shared-memory multiprocessor system","authors":"I. Onyuksel","doi":"10.1109/PCCC.1992.200536","DOIUrl":"https://doi.org/10.1109/PCCC.1992.200536","url":null,"abstract":"Two different approximate state models are presented for the performance analysis of a shared-memory multiprocessor system. The steady-state solutions for the state transition matrices were obtained by applying an iterative numerical technique. The numerical results illustrate that the state models produce less than 5% approximation error compared to simulation results. It has been observed that the coefficient of variation for the service time of the shared memory has little effect on the system performance.<<ETX>>","PeriodicalId":250212,"journal":{"name":"Eleventh Annual International Phoenix Conference on Computers and Communication [1992 Conference Proceedings]","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126510614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-01DOI: 10.1109/PCCC.1992.200589
Chang Chen, Yoshiaki Kakuda, T. Kikuno
A new technique for reconfiguration of a fault-tolerant linear array that is constructed by connecting multiple modular redundant processors is proposed. The array has the following characteristics: a fault of any copy of each processor can be masked without the need for reconfiguration, and the array can be efficiently reconfigured for maximizing the capability to detect and correct any future faults when some voters and copies of processors fail. The reconfiguration problem for the array is formalized, and a linear time algorithm for the reconfiguration is proposed. An extension of the reconfiguration problem and its algorithm are discussed.<>
{"title":"An assignment algorithm for reconfiguration of fault tolerant linear array","authors":"Chang Chen, Yoshiaki Kakuda, T. Kikuno","doi":"10.1109/PCCC.1992.200589","DOIUrl":"https://doi.org/10.1109/PCCC.1992.200589","url":null,"abstract":"A new technique for reconfiguration of a fault-tolerant linear array that is constructed by connecting multiple modular redundant processors is proposed. The array has the following characteristics: a fault of any copy of each processor can be masked without the need for reconfiguration, and the array can be efficiently reconfigured for maximizing the capability to detect and correct any future faults when some voters and copies of processors fail. The reconfiguration problem for the array is formalized, and a linear time algorithm for the reconfiguration is proposed. An extension of the reconfiguration problem and its algorithm are discussed.<<ETX>>","PeriodicalId":250212,"journal":{"name":"Eleventh Annual International Phoenix Conference on Computers and Communication [1992 Conference Proceedings]","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130209410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-01DOI: 10.1109/PCCC.1992.200539
D. Jayasimha
Latency and synchronization overheads have been identified as two fundamental problems in large-scale shared memory multiprocessors. The notion of partial sharing of variables is introduced, and architectures based on hierarchical memories which exploit this notion of partial sharing to reduce the latency and synchronization overheads significantly are suggested. A particular class of architectures, the tree structure, hierarchical memory multiprocessor architectures (THMMs), is examined by suggesting an implementation and considering the execution and the performance of several well-known applications such as matrix multiplication, solution of partial differential equations, solution of linear recurrence relations, barrier synchronization, and reduction operations. Speedup and cost figures for these examples are compared when executing on the THMM and on a conventional memory multiprocessor.<>
{"title":"Partially shared variables and hierarchical shared memory multiprocessor architectures","authors":"D. Jayasimha","doi":"10.1109/PCCC.1992.200539","DOIUrl":"https://doi.org/10.1109/PCCC.1992.200539","url":null,"abstract":"Latency and synchronization overheads have been identified as two fundamental problems in large-scale shared memory multiprocessors. The notion of partial sharing of variables is introduced, and architectures based on hierarchical memories which exploit this notion of partial sharing to reduce the latency and synchronization overheads significantly are suggested. A particular class of architectures, the tree structure, hierarchical memory multiprocessor architectures (THMMs), is examined by suggesting an implementation and considering the execution and the performance of several well-known applications such as matrix multiplication, solution of partial differential equations, solution of linear recurrence relations, barrier synchronization, and reduction operations. Speedup and cost figures for these examples are compared when executing on the THMM and on a conventional memory multiprocessor.<<ETX>>","PeriodicalId":250212,"journal":{"name":"Eleventh Annual International Phoenix Conference on Computers and Communication [1992 Conference Proceedings]","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130572326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-01DOI: 10.1109/PCCC.1992.200514
L. Clark, R. Grondin, S. Dey
The application of ferroelectric thin-film capacitors as synapses in integrated circuit implementation of artificial neural networks is described. A continuous-valued synapse where the synaptic efficacy is controlled by the polarization of a ferroelectric capacitor element is presented. The ferroelectric analog synapse utilizes nondestructive readout. A ferroelectric capacitor circuit model has been added to the SPICE circuit simulation program and is complete with respect to current vs. time, polarization, and current vs. voltage responses. The simulated response in characterization circuits is shown to closely model that of lead zirconate titanate (PZT) thin-film capacitors. Simulation and experimental results show the proposed synapse circuit to possess a number of favorable characteristics, including very infrequent refresh and fine programming granularity.<>
{"title":"Integrated circuit neural networks using ferroelectric analog memory","authors":"L. Clark, R. Grondin, S. Dey","doi":"10.1109/PCCC.1992.200514","DOIUrl":"https://doi.org/10.1109/PCCC.1992.200514","url":null,"abstract":"The application of ferroelectric thin-film capacitors as synapses in integrated circuit implementation of artificial neural networks is described. A continuous-valued synapse where the synaptic efficacy is controlled by the polarization of a ferroelectric capacitor element is presented. The ferroelectric analog synapse utilizes nondestructive readout. A ferroelectric capacitor circuit model has been added to the SPICE circuit simulation program and is complete with respect to current vs. time, polarization, and current vs. voltage responses. The simulated response in characterization circuits is shown to closely model that of lead zirconate titanate (PZT) thin-film capacitors. Simulation and experimental results show the proposed synapse circuit to possess a number of favorable characteristics, including very infrequent refresh and fine programming granularity.<<ETX>>","PeriodicalId":250212,"journal":{"name":"Eleventh Annual International Phoenix Conference on Computers and Communication [1992 Conference Proceedings]","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132155098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-01DOI: 10.1109/PCCC.1992.200590
Shun-Shii Lin, F. Lin
A multiple-fault diagnosis procedure which used three distinct test vectors to diagnose a 4*4 baseline network is presented. Multistage interconnection networks are briefly introduced, and the fault model is given. The necessary and sufficient conditions are derived for the input test vectors to diagnose a single switching element. It is proved that six tests are necessary and sufficient to diagnose a 4*4 and an 8*8 baseline network. A multiple-fault diagnosis procedure for an N*N baseline network is presented by using only 2 log/sub 2/ N tests.<>
{"title":"On multiple-fault diagnosis of baseline interconnection networks","authors":"Shun-Shii Lin, F. Lin","doi":"10.1109/PCCC.1992.200590","DOIUrl":"https://doi.org/10.1109/PCCC.1992.200590","url":null,"abstract":"A multiple-fault diagnosis procedure which used three distinct test vectors to diagnose a 4*4 baseline network is presented. Multistage interconnection networks are briefly introduced, and the fault model is given. The necessary and sufficient conditions are derived for the input test vectors to diagnose a single switching element. It is proved that six tests are necessary and sufficient to diagnose a 4*4 and an 8*8 baseline network. A multiple-fault diagnosis procedure for an N*N baseline network is presented by using only 2 log/sub 2/ N tests.<<ETX>>","PeriodicalId":250212,"journal":{"name":"Eleventh Annual International Phoenix Conference on Computers and Communication [1992 Conference Proceedings]","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131980819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-01DOI: 10.1109/PCCC.1992.200603
F. Sato, I. Imai, K. Katsuyama, T. Mizuno
SuperC/sup 2/, a concurrent object-oriented language designed for the implementation of distributed software running on a network of computers, is described. The goal of superC/sup 2/ is to estimate the easiness of programming of distributed systems and harmony between the distributed systems and programming language. The design policy, basic ideas, and implementation issues for superC/sup 2/ are considered. Examples of the use of superC/sup 2/ and some discussions on the development environment are also presented. Although the first version of superC/sup 2/ only extended the concurrent processing facilities, the current version has extended the facilities to store the object to the file storage persistently. These facilities supply the basis of the distributed object-oriented database. SuperC/sup 2/ can manage the distributed objects by their name. Using these facilities, superC/sup 2/ provides a unified access method to the interprocess communication and file system.<>
{"title":"Development of the concurrent object-oriented language superC2","authors":"F. Sato, I. Imai, K. Katsuyama, T. Mizuno","doi":"10.1109/PCCC.1992.200603","DOIUrl":"https://doi.org/10.1109/PCCC.1992.200603","url":null,"abstract":"SuperC/sup 2/, a concurrent object-oriented language designed for the implementation of distributed software running on a network of computers, is described. The goal of superC/sup 2/ is to estimate the easiness of programming of distributed systems and harmony between the distributed systems and programming language. The design policy, basic ideas, and implementation issues for superC/sup 2/ are considered. Examples of the use of superC/sup 2/ and some discussions on the development environment are also presented. Although the first version of superC/sup 2/ only extended the concurrent processing facilities, the current version has extended the facilities to store the object to the file storage persistently. These facilities supply the basis of the distributed object-oriented database. SuperC/sup 2/ can manage the distributed objects by their name. Using these facilities, superC/sup 2/ provides a unified access method to the interprocess communication and file system.<<ETX>>","PeriodicalId":250212,"journal":{"name":"Eleventh Annual International Phoenix Conference on Computers and Communication [1992 Conference Proceedings]","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123802028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-01DOI: 10.1109/PCCC.1992.200608
J. Berner, K. M. Ware
A new ground based receiver for deep space applications is being designed. By utilizing high speed gallium arsenide applications specific integrated circuits, advanced single board computers, and a real-time embedded operating system, the Block V Receiver will dramatically reduce the volume of equipment at a tracking complex, yet will provide new capabilities with higher reliability. A digital demodulator is the core of the receiver. The system architecture is described. The complexity of the design requires extensive use of both computer aided engineering (CAE) tools and computer aided software engineering (CASE) tools to ensure success. CAE and CASE tools are being used to perform system simulation, hardware design and simulation, and software design, frame generation, and configuration control.<>
{"title":"An extremely sensitive digital receiver for deep space satellite communications","authors":"J. Berner, K. M. Ware","doi":"10.1109/PCCC.1992.200608","DOIUrl":"https://doi.org/10.1109/PCCC.1992.200608","url":null,"abstract":"A new ground based receiver for deep space applications is being designed. By utilizing high speed gallium arsenide applications specific integrated circuits, advanced single board computers, and a real-time embedded operating system, the Block V Receiver will dramatically reduce the volume of equipment at a tracking complex, yet will provide new capabilities with higher reliability. A digital demodulator is the core of the receiver. The system architecture is described. The complexity of the design requires extensive use of both computer aided engineering (CAE) tools and computer aided software engineering (CASE) tools to ensure success. CAE and CASE tools are being used to perform system simulation, hardware design and simulation, and software design, frame generation, and configuration control.<<ETX>>","PeriodicalId":250212,"journal":{"name":"Eleventh Annual International Phoenix Conference on Computers and Communication [1992 Conference Proceedings]","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127159436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-01DOI: 10.1109/PCCC.1992.200510
K. Maly, F. Paterra, C. M. Overstreet, R. Mukkamala, S. Khanna
A method for using existing networks and available parallel channels to provide the needed throughput for remote visualization is proposed. This method keeps the functionalities of the traditional protocol stack but introduces parallelism at all points where bottlenecks can develop. The approach allows the use of existing protocol standards and off-the-shelf hardware to permit new applications that require higher bandwidths. The design tradeoffs in this approach are discussed to develop working architectures needed to solve the animation problems of 5, 10, and 33 frames/s, or 10 Mb every 200 ms, 100 ms, and 30 ms, respectively.<>
{"title":"Remote visualization and parallelism using existing networks","authors":"K. Maly, F. Paterra, C. M. Overstreet, R. Mukkamala, S. Khanna","doi":"10.1109/PCCC.1992.200510","DOIUrl":"https://doi.org/10.1109/PCCC.1992.200510","url":null,"abstract":"A method for using existing networks and available parallel channels to provide the needed throughput for remote visualization is proposed. This method keeps the functionalities of the traditional protocol stack but introduces parallelism at all points where bottlenecks can develop. The approach allows the use of existing protocol standards and off-the-shelf hardware to permit new applications that require higher bandwidths. The design tradeoffs in this approach are discussed to develop working architectures needed to solve the animation problems of 5, 10, and 33 frames/s, or 10 Mb every 200 ms, 100 ms, and 30 ms, respectively.<<ETX>>","PeriodicalId":250212,"journal":{"name":"Eleventh Annual International Phoenix Conference on Computers and Communication [1992 Conference Proceedings]","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116734854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-01DOI: 10.1109/PCCC.1992.200597
L. Gowen, J. Collofello, F. Calliss
The authors identify strategies for conducting preliminary software hazard analysis, which includes software hazard identification, documentation, and review. The goal for such strategies is to improve a system's overall safety by increasing the hazard list's completeness, correctness, and preciseness. Along with presenting these strategies, a framework is introduced for applying them to safety-critical software development. Before explaining the framework and its related strategies, relevant background issues that relate to safety are discussed.<>
{"title":"Preliminary hazard analysis for safety-critical software systems","authors":"L. Gowen, J. Collofello, F. Calliss","doi":"10.1109/PCCC.1992.200597","DOIUrl":"https://doi.org/10.1109/PCCC.1992.200597","url":null,"abstract":"The authors identify strategies for conducting preliminary software hazard analysis, which includes software hazard identification, documentation, and review. The goal for such strategies is to improve a system's overall safety by increasing the hazard list's completeness, correctness, and preciseness. Along with presenting these strategies, a framework is introduced for applying them to safety-critical software development. Before explaining the framework and its related strategies, relevant background issues that relate to safety are discussed.<<ETX>>","PeriodicalId":250212,"journal":{"name":"Eleventh Annual International Phoenix Conference on Computers and Communication [1992 Conference Proceedings]","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132045418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-01DOI: 10.1109/PCCC.1992.200605
B. Freeman-Benson, M. Wilson, A. Borning
The DeltaStar incremental algorithm for solving constraint hierarchies, which was developed as part of a continuing investigation on the design and implementation of constraint programming languages, is described. DeltaStar is a framework for incremental solvers built above an existing flat solver that provides the constraint solving techniques. By plugging different flat solvers into DeltaStar, different hierarchical solvers can quickly be produced and experimented with. Two implementations of DeltaStar, as well as previous algorithms that can be viewed as instances of DeltaStar, are discussed.<>
{"title":"DeltaStar: a general algorithm for incremental satisfaction of constraint hierarchies","authors":"B. Freeman-Benson, M. Wilson, A. Borning","doi":"10.1109/PCCC.1992.200605","DOIUrl":"https://doi.org/10.1109/PCCC.1992.200605","url":null,"abstract":"The DeltaStar incremental algorithm for solving constraint hierarchies, which was developed as part of a continuing investigation on the design and implementation of constraint programming languages, is described. DeltaStar is a framework for incremental solvers built above an existing flat solver that provides the constraint solving techniques. By plugging different flat solvers into DeltaStar, different hierarchical solvers can quickly be produced and experimented with. Two implementations of DeltaStar, as well as previous algorithms that can be viewed as instances of DeltaStar, are discussed.<<ETX>>","PeriodicalId":250212,"journal":{"name":"Eleventh Annual International Phoenix Conference on Computers and Communication [1992 Conference Proceedings]","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133418640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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