Pub Date : 2018-06-01DOI: 10.1109/3DPEIM.2018.8525233
Hao Zhang, S. Noh, N. Asatani, Yukiharu Kimoto, A. Suetake, S. Nagao, T. Sugahara, K. Suganuma
We introduce low temperature/pressure Ag-Ag direct bonding method for a high-temperature die-attachment structure, which joins SiC dummy chips and direct bonded copper (DBC) substrates. The process uses "nano-volcanic eruption of Ag" caused by stress migration at 250 °C. Neither joining paste nor solder is required. The bonding achieved a die-shear strength over 110 MPa. Only a pre-sputtered Ag thin layer on the surface of dummy chips and DBC substrates can realize bonding with a low pressure (1.0 MPa) provided by a simple bonding jig at 250 °C. The formed Ag joint has a joint layer thickness of less than 4 μm, whose density is similar to that of bulk silver. This feature realizes the ultra-high bonding strength as well as an ideal electric/thermal performance. The SMB technique is well compatible with the current die-attachment process for power-devices. This breakthrough achievement will bring a bright future to the development of next generation power devices with ultra-high performance and reliability.
{"title":"Nearly perfect Ag joints prepared by Ag stress-migration-bonding (SMB) process","authors":"Hao Zhang, S. Noh, N. Asatani, Yukiharu Kimoto, A. Suetake, S. Nagao, T. Sugahara, K. Suganuma","doi":"10.1109/3DPEIM.2018.8525233","DOIUrl":"https://doi.org/10.1109/3DPEIM.2018.8525233","url":null,"abstract":"We introduce low temperature/pressure Ag-Ag direct bonding method for a high-temperature die-attachment structure, which joins SiC dummy chips and direct bonded copper (DBC) substrates. The process uses \"nano-volcanic eruption of Ag\" caused by stress migration at 250 °C. Neither joining paste nor solder is required. The bonding achieved a die-shear strength over 110 MPa. Only a pre-sputtered Ag thin layer on the surface of dummy chips and DBC substrates can realize bonding with a low pressure (1.0 MPa) provided by a simple bonding jig at 250 °C. The formed Ag joint has a joint layer thickness of less than 4 μm, whose density is similar to that of bulk silver. This feature realizes the ultra-high bonding strength as well as an ideal electric/thermal performance. The SMB technique is well compatible with the current die-attachment process for power-devices. This breakthrough achievement will bring a bright future to the development of next generation power devices with ultra-high performance and reliability.","PeriodicalId":262974,"journal":{"name":"2018 Second International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123316233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/3DPEIM.2018.8525239
Weihua Shao, L. Ran, Zheng Zeng, R. Wu, P. Mawby, Jiang Huaping, D. Kastha, P. Bajpai
The current requirement of a pulsed load may be many times of the average value. To prevent over temperature, short-term over current capability is needed. The over current capability of existing power modules is barely a few microseconds, which is mainly constrained by the junction temperature. This study customizes a power module with enhanced short-term current capability using phase change material (PCM). Thanks to the great thermal capacity of PCM during melting, the power module can support pulsed load three times the rated value for tens of seconds with appropriate PCM. To avoid unacceptably increasing thermal resistance, a metal framework is utilized. Two different 3D printed metal frameworks are presented and compared. Device power losses in a grid-connected inverter is calculated, followed by the thermal model for this case study. Simulation is conducted to show the effects of PCM thickness and proportion concerning the phase change time, dynamic thermal response and steady state thermal resistance, followed by the optimization of design using finite element analyses (FEA). Finally, the effect of the PCM is verified through experiment. When the junction temperature of the device is controlled below the limit, the power module can indeed handle the required large current for an intended duration.
{"title":"Power Modules for Pulsed Power Applications Using Phase Change Material","authors":"Weihua Shao, L. Ran, Zheng Zeng, R. Wu, P. Mawby, Jiang Huaping, D. Kastha, P. Bajpai","doi":"10.1109/3DPEIM.2018.8525239","DOIUrl":"https://doi.org/10.1109/3DPEIM.2018.8525239","url":null,"abstract":"The current requirement of a pulsed load may be many times of the average value. To prevent over temperature, short-term over current capability is needed. The over current capability of existing power modules is barely a few microseconds, which is mainly constrained by the junction temperature. This study customizes a power module with enhanced short-term current capability using phase change material (PCM). Thanks to the great thermal capacity of PCM during melting, the power module can support pulsed load three times the rated value for tens of seconds with appropriate PCM. To avoid unacceptably increasing thermal resistance, a metal framework is utilized. Two different 3D printed metal frameworks are presented and compared. Device power losses in a grid-connected inverter is calculated, followed by the thermal model for this case study. Simulation is conducted to show the effects of PCM thickness and proportion concerning the phase change time, dynamic thermal response and steady state thermal resistance, followed by the optimization of design using finite element analyses (FEA). Finally, the effect of the PCM is verified through experiment. When the junction temperature of the device is controlled below the limit, the power module can indeed handle the required large current for an intended duration.","PeriodicalId":262974,"journal":{"name":"2018 Second International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132458003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/3DPEIM.2018.8525238
Bo Gao, Xin Zhao, D. Hopkins
Electrical and thermal performance of rigid PCB based voltage regulator modules (VRMs) are modeled and simulated with FEA Multiphysics simulation tool. Then, a new concept of building power converters on folded flexible substrates is proposed to solve the issues existing in previous solutions. The newly proposed concept is then analyzed, simulated and compared with previous ones. A converter phase block implements the proposed concept was designed, built and tested. Test result shows at 2.5MHz, 12V to 1.2V 40A operation, the proposed converter can achieve 62.5A/cm2 planar power density and the measured module temperature is only 3.06°C above heat sink temperature.
{"title":"Increasing Electrical and Thermal Performances of VRMs by Using Folded Flexible Substrate","authors":"Bo Gao, Xin Zhao, D. Hopkins","doi":"10.1109/3DPEIM.2018.8525238","DOIUrl":"https://doi.org/10.1109/3DPEIM.2018.8525238","url":null,"abstract":"Electrical and thermal performance of rigid PCB based voltage regulator modules (VRMs) are modeled and simulated with FEA Multiphysics simulation tool. Then, a new concept of building power converters on folded flexible substrates is proposed to solve the issues existing in previous solutions. The newly proposed concept is then analyzed, simulated and compared with previous ones. A converter phase block implements the proposed concept was designed, built and tested. Test result shows at 2.5MHz, 12V to 1.2V 40A operation, the proposed converter can achieve 62.5A/cm2 planar power density and the measured module temperature is only 3.06°C above heat sink temperature.","PeriodicalId":262974,"journal":{"name":"2018 Second International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM)","volume":"113 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114003229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/3DPEIM.2018.8525237
A. Hanif, Faisal Khan
A reflectometry based non-interfering method to identify the degradation of a buck converter built from SiC MOSFET has been proposed in this paper, and spread spectrum time domain reflectometry (SSTDR) has been applied between gate and source terminal to achieve the in-situ state of health (SOH) estimation. A controlled aging station was used to execute the power cycling method to age the SiC MOSFET. SSTDR reflections were recorded for both the healthy and the aged buck converter, and these recorded values were compared to determine the level of degradation. Through the experiment, it was apparent that a single measurement is sufficient to estimate the degradation level associated to the SiC MOSFET in a live buck converter having complex/branch network. The outcome of this research also proves that the SSTDR based technique can identify the aging of other components in the system. Since the gate terminal always stays at lower potential and easier to access, this technique brings an added advantage to the existing condition monitoring schemes.
{"title":"Reflectometry Based SOH Estimation Scheme for a SiC Buck Converter Having Branched Network","authors":"A. Hanif, Faisal Khan","doi":"10.1109/3DPEIM.2018.8525237","DOIUrl":"https://doi.org/10.1109/3DPEIM.2018.8525237","url":null,"abstract":"A reflectometry based non-interfering method to identify the degradation of a buck converter built from SiC MOSFET has been proposed in this paper, and spread spectrum time domain reflectometry (SSTDR) has been applied between gate and source terminal to achieve the in-situ state of health (SOH) estimation. A controlled aging station was used to execute the power cycling method to age the SiC MOSFET. SSTDR reflections were recorded for both the healthy and the aged buck converter, and these recorded values were compared to determine the level of degradation. Through the experiment, it was apparent that a single measurement is sufficient to estimate the degradation level associated to the SiC MOSFET in a live buck converter having complex/branch network. The outcome of this research also proves that the SSTDR based technique can identify the aging of other components in the system. Since the gate terminal always stays at lower potential and easier to access, this technique brings an added advantage to the existing condition monitoring schemes.","PeriodicalId":262974,"journal":{"name":"2018 Second International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM)","volume":"361 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116359398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/3dpeim.2018.8525232
S. Noh, Hao Zhang, K. Suganuma
In this work, efforts were made to prepare a thermostable die-attach structure which includes stable sintered porous Ag and multi-layer surface metallization. Silicon carbide particles (SiCp) were added into the Ag sintering paste to improve the high-temperature reliability of sintered Ag joints. Presence of SiCp in the bonding structures inhibited the coarsening of the porous Ag network during high temperature storage (HTS) tests, and the morphology remains similar to that of the as-sintered state. In addition to the Ag paste, on the side of DBC substrates, the thermal reliability of various surface metallization such as Ni, Ti and Pt were also evaluated by shear strength, cross-section morphology and on-resistance test. The results indicated that Ti and Pt diffusion barrier layers played an active role in inhibiting the oxidation of Cu and inter-diffusion between Cu and Ag at high temperatures exceeding 250 °C. While Ni barrier layer showed a relatively weak barrier effect due to the generation of thin oxide layer between Ag and Ni. The changes of on-resistance indicated that Pt metallization has a relatively better electrical property comparing to that of Ti and Ni. Ag metallization which lacks of barrier layers showed a severe growth of oxide layer between Ag and Cu, however, the on-resistance showed less changes, which needs further studies.
{"title":"Thermostable porous Ag die-attach structure for high-temperature power devices","authors":"S. Noh, Hao Zhang, K. Suganuma","doi":"10.1109/3dpeim.2018.8525232","DOIUrl":"https://doi.org/10.1109/3dpeim.2018.8525232","url":null,"abstract":"In this work, efforts were made to prepare a thermostable die-attach structure which includes stable sintered porous Ag and multi-layer surface metallization. Silicon carbide particles (SiCp) were added into the Ag sintering paste to improve the high-temperature reliability of sintered Ag joints. Presence of SiCp in the bonding structures inhibited the coarsening of the porous Ag network during high temperature storage (HTS) tests, and the morphology remains similar to that of the as-sintered state. In addition to the Ag paste, on the side of DBC substrates, the thermal reliability of various surface metallization such as Ni, Ti and Pt were also evaluated by shear strength, cross-section morphology and on-resistance test. The results indicated that Ti and Pt diffusion barrier layers played an active role in inhibiting the oxidation of Cu and inter-diffusion between Cu and Ag at high temperatures exceeding 250 °C. While Ni barrier layer showed a relatively weak barrier effect due to the generation of thin oxide layer between Ag and Ni. The changes of on-resistance indicated that Pt metallization has a relatively better electrical property comparing to that of Ti and Ni. Ag metallization which lacks of barrier layers showed a severe growth of oxide layer between Ag and Cu, however, the on-resistance showed less changes, which needs further studies.","PeriodicalId":262974,"journal":{"name":"2018 Second International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134467278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/3dpeim.2018.8525230
{"title":"3D-PEIM 2018 Copyright Page","authors":"","doi":"10.1109/3dpeim.2018.8525230","DOIUrl":"https://doi.org/10.1109/3dpeim.2018.8525230","url":null,"abstract":"","PeriodicalId":262974,"journal":{"name":"2018 Second International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122283953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/3DPEIM.2018.8525234
J. P. Kozak, K. Ngo, D. DeVoto, J. Major
Integrating SiC power MOSFETs is very attractive for advancing power electronic system performance, yet the system reliability with new devices remains in question. This work presents an overview of accelerated lifetime tests and the packaging and semiconductor failure mechanisms they excite. The experiments explained here includes High Temperature Gate Bias (HTGB), Switching Cycling, Power Cycling, and Thermal Cycling. These experiments stress different failure mechanisms, that show degradation in different device parameters including, but not limited to, threshold voltage and on-resistance. These four experiments help illustrate the spectrum between device and package degradation that can be used to design more reliable power electronic circuits.
{"title":"Impact of Accelerated Stress-Tests on SiC MOSFET Precursor Parameters","authors":"J. P. Kozak, K. Ngo, D. DeVoto, J. Major","doi":"10.1109/3DPEIM.2018.8525234","DOIUrl":"https://doi.org/10.1109/3DPEIM.2018.8525234","url":null,"abstract":"Integrating SiC power MOSFETs is very attractive for advancing power electronic system performance, yet the system reliability with new devices remains in question. This work presents an overview of accelerated lifetime tests and the packaging and semiconductor failure mechanisms they excite. The experiments explained here includes High Temperature Gate Bias (HTGB), Switching Cycling, Power Cycling, and Thermal Cycling. These experiments stress different failure mechanisms, that show degradation in different device parameters including, but not limited to, threshold voltage and on-resistance. These four experiments help illustrate the spectrum between device and package degradation that can be used to design more reliable power electronic circuits.","PeriodicalId":262974,"journal":{"name":"2018 Second International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129609925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/3dpeim.2018.8525235
{"title":"3D-PEIM 2018 Cover Page","authors":"","doi":"10.1109/3dpeim.2018.8525235","DOIUrl":"https://doi.org/10.1109/3dpeim.2018.8525235","url":null,"abstract":"","PeriodicalId":262974,"journal":{"name":"2018 Second International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126887672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/3DPEIM.2018.8525231
T. Takemasa, J. Jiu, Junko Seino, K. Suganuma
Wide-bang gap (WBG) semiconductors such as SiC and GaN have many advantages including energy saving and high power capability and are expected as the new semiconductors substituting traditional Si. To bond these SiC/GaN dies to substrates securely, the die-bonding materials are required to stand high-temperature environment and possess superior heat and electronic-conducting properties as well as excellent reliability. Recently, Ag micron particle paste has been developed to show good performance such as high-temperature raliability and high electronic conductivity. Direct copper bonding (DCB) is the commonly used substrate, of which a Cu face is bonded with dies. Since Cu is easy to be oxidized in air, the substrates have to be coated with a thin layer of Ag to realize bonding and to improve the mechanical property. In this work, a simple two-step sintering process was proposed to omit the complicated Ag-coating process and achieve the stable direct bonding between a Cu surface and a die. The two-steps sintering process included first-step in the air and second-step in hydrogen atmosphere. Shear strength over 20 MPa has been achieved by an opti-mized sintering condition with an affordable Ag micron paste.
{"title":"Improvement of Ag sintering Quality on Cu surface at Hydrogen atmosphere","authors":"T. Takemasa, J. Jiu, Junko Seino, K. Suganuma","doi":"10.1109/3DPEIM.2018.8525231","DOIUrl":"https://doi.org/10.1109/3DPEIM.2018.8525231","url":null,"abstract":"Wide-bang gap (WBG) semiconductors such as SiC and GaN have many advantages including energy saving and high power capability and are expected as the new semiconductors substituting traditional Si. To bond these SiC/GaN dies to substrates securely, the die-bonding materials are required to stand high-temperature environment and possess superior heat and electronic-conducting properties as well as excellent reliability. Recently, Ag micron particle paste has been developed to show good performance such as high-temperature raliability and high electronic conductivity. Direct copper bonding (DCB) is the commonly used substrate, of which a Cu face is bonded with dies. Since Cu is easy to be oxidized in air, the substrates have to be coated with a thin layer of Ag to realize bonding and to improve the mechanical property. In this work, a simple two-step sintering process was proposed to omit the complicated Ag-coating process and achieve the stable direct bonding between a Cu surface and a die. The two-steps sintering process included first-step in the air and second-step in hydrogen atmosphere. Shear strength over 20 MPa has been achieved by an opti-mized sintering condition with an affordable Ag micron paste.","PeriodicalId":262974,"journal":{"name":"2018 Second International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124534487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/3DPEIM.2018.8525236
C. Buttay, C. Martin, F. Morel, Remy Caillaud, Johan Le Leslé, R. Mrad, N. Degrenne, S. Mollov
The embedding of components in Printed Circuit Board (PCB) material is an attractive solution to improve the performance of power converters in the 1 W–100 kW range by increasing the power density (exploitation of unused volume in the PCB), reducing circuit parasitics (strip-line approach to current distribution, shorter interconnects), and improving manufacturability (rationalization of the manufacturing process, automation). This paper presents a review of the embedding technologies, with a special focus on power components (passive, active) and thermal mangement. The second part of the article is dedicated to the design process, and proposes a new design approach, inspired from microelectronics. The ambition is to simplify the design process by using "design toolkits". These toolkits would provide the designer with elements such as design rules, libraries or models. The objective is to enable automatic design validation, and to ensure the design can be produced directly.
{"title":"Application of the PCB-Embedding Technology in Power Electronics – State of the Art and Proposed Development","authors":"C. Buttay, C. Martin, F. Morel, Remy Caillaud, Johan Le Leslé, R. Mrad, N. Degrenne, S. Mollov","doi":"10.1109/3DPEIM.2018.8525236","DOIUrl":"https://doi.org/10.1109/3DPEIM.2018.8525236","url":null,"abstract":"The embedding of components in Printed Circuit Board (PCB) material is an attractive solution to improve the performance of power converters in the 1 W–100 kW range by increasing the power density (exploitation of unused volume in the PCB), reducing circuit parasitics (strip-line approach to current distribution, shorter interconnects), and improving manufacturability (rationalization of the manufacturing process, automation). This paper presents a review of the embedding technologies, with a special focus on power components (passive, active) and thermal mangement. The second part of the article is dedicated to the design process, and proposes a new design approach, inspired from microelectronics. The ambition is to simplify the design process by using \"design toolkits\". These toolkits would provide the designer with elements such as design rules, libraries or models. The objective is to enable automatic design validation, and to ensure the design can be produced directly.","PeriodicalId":262974,"journal":{"name":"2018 Second International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130680629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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